Texas Instruments TPS71H50QPWPR, TPS71H50QPWPLE, TPS71H48QPWPR, TPS71H48QPWPLE, TPS71H33QPWPR Datasheet

PWP PACKAGE

(BOTTOM VIEW)

Thermal

Pad

NC ± No internal connection

² SENSE ± Fixed voltage options only (TPS71H33,

TPS71H48, and TPS71H50)

³ FB ± Adjustable version only (TPS71H01)

TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q LOW-DROPOUT VOLTAGE REGULATORS

SLVS152A ± NOVEMBER 1996 ± REVISED JANUARY 1997

DAvailable in 5-V, 4.85-V, and 3.3-V Fixed-Output and Adjustable Versions

DVery Low-Dropout Voltage . . . Maximum of 32 mV at IO = 100 mA (TPS71H50)

DVery Low Quiescent Current ± Independent of Load . . . 285 μA Typ

DExtremely Low Sleep-State Current

0.5μA Max

D2% Tolerance Over Specified Conditions For Fixed-Output Versions

DOutput Current Range of 0 mA to 500 mA

DTSSOP Package Option Offers Reduced Component Height for Space-Critical Applications

PWP PACKAGE

(TOP VIEW)

GND/HEATSINK			1	20			GND/HEATSINK
GND/HEATSINK			2	19			GND/HEATSINK
GND			3	18			NC
NC			4	17			NC
EN			5	16			PG
IN			6	15			SENSE² /FB³
IN			7	14			OUT
NC			8	13			OUT
GND/HEATSINK			9	12			GND/HEATSINK
GND/HEATSINK			10	11			GND/HEATSINK

DThermally Enhanced Surface-Mount Package

DPower-Good (PG) Status Output

description

The TPS71Hxx integrated circuits are a family of micropower low-dropout (LDO) voltage regulators. An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 32 mV at an output current of 100 mA for the TPS71H50) and is directly

proportional to the output current (see Figure 1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and remains independent of output loading (typically 285 μA over the full range of output current, 0 mA to 500 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems. The LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 0.5 μA maximum at TJ = 25°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q

LOW-DROPOUT VOLTAGE REGULATORS

SLVS152A ± NOVEMBER 1996 ± REVISED JANUARY 1997

description (continued)

	0.25
		TA = 25°C
	0.2
± V	0.15				TPS71H33
Voltage
							TPS71H48
	0.1
Dropout								TPS71H50
	0.05
	0							0.35	0.4	0.45	0.5
	0	0.05	0.1	0.15	0.2	0.25	0.3
				IO ± Output Current ± A

Figure 1. Dropout Voltage Versus Output Current

Power good (PG) reports low output voltage and can be used to implement a power-on reset or a low-battery indicator.

The TPS71Hxx is offered in 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for adjustable version). The TPS71Hxx family is available in a TSSOP (20-pin) thermally enhanced surface-mount power package. The package has an innovative thermal pad that, when soldered to the printed-wiring board (PWB), enables the device to dissipate several watts of power (see Thermal Information section). Maximum height of the package is 1.2 mm.

AVAILABLE OPTIONS

		OUTPUT VOLTAGE			TSSOP
	TJ		(V)
					(PWP)
		MIN	TYP	MAX
		4.9	5	5.1	TPS71H50QPWPLE
		4.75	4.85	4.95	TPS71H48QPWPLE
	± 55°C to 150°C
		3.23	3.3	3.37	TPS71H33QPWPLE
		Adjustable²			TPS71H01QPWPLE
		1.2 V to 9.75 V

²The PWP package is only available left-end taped and reeled, as indicated by the LE suffix on the device type. The TPS71H01Q is programmable using an external resistor divider (see application information).

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q

LOW-DROPOUT VOLTAGE REGULATORS

SLVS152A ± NOVEMBER 1996 ± REVISED JANUARY 1997

	TPS71Hxx²
VI	8			20	PG
	IN		PG
	9			15
	IN	SENSE
	10			14	VO
	IN		OUT
0.1 μF	6		OUT	13
	EN				CO³
				+
		GND		10	μF
	1	2	3	CSR

² TPS71H33, TPS71H48, TPS71H50 (fixed-voltage options)

³Capacitor selection is nontrivial. See application information section for details.

Figure 2. Typical Application Configuration

functional block diagram

IN				RESISTOR DIVIDER OPTIONS
²	²	²		DEVICE	R1	R2	UNIT
EN
				TPS71H01	0	∞	Ω
			PG	TPS71H33	420	233	kΩ
				TPS71H48	726	233	kΩ
_				TPS71H50	756	233	kΩ
+				NOTE A: Resistors are nominal values only.
			OUT
					COMPONENT COUNT

1.12 V	+	SENSE³ /FB	MOS transistors	464
			Bilpolar transistors	41
	_
		R1	Diodes	4
Vref = 1.178 V
			Capacitors	17
			Resistors	76
		R2

GND

² Switch positions are shown with EN low (active).

³For most applications, SENSE should be externally connected to OUT as close as possible to the device. (For other implementations, refer to SENSE-pin connection discussion in Applications Information section.)

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q

LOW-DROPOUT VOLTAGE REGULATORS

SLVS152A ± NOVEMBER 1996 ± REVISED JANUARY 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Input voltage range³ , V , PG, SENSE,	EN . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . ±0.3 V to 11	V
I
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2	A
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			See Dissipation Rating Tables 1 and 2
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . ±55°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . ±65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . .			. . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

³ All voltage values are with respect to network terminal ground.

DISSIPATION RATING TABLE 1 ± FREE-AIR TEMPERATURE (see Figure 3)§

	PACKAGE	TA ≤ 25°C	DERATING FACTOR	TA = 70°C	TA = 125°C
		POWER RATING	ABOVE TA = 25°C	POWER RATING	POWER RATING
	PWP¶	700 mW	5.6 mW/°C	448 mW	140 mW
	DISSIPATION RATING TABLE 2 ± CASE TEMPERATURE (see Figure 4)§
	PACKAGE	TC ≤ 62.5°C	DERATING FACTOR	TC = 70°C	TC = 125°C
		POWER RATING	ABOVE TC = 62.5°C	POWER RATING	POWER RATING
	PWP¶	25 W	285.7 mW/°C	22.9 W	7.1 W

§Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C. For guidelines on maintaining junction temperature within recommended operating range, see the Thermal Information section.

¶Refer to Thermal Information section for detailed power dissipation considerations when using the

TSSOP packages.

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q LOW-DROPOUT VOLTAGE REGULATORS

SLVS152A ± NOVEMBER 1996 ± REVISED JANUARY 1997

PD ± Maximum Continuous Dissipation ± mW

		DISSIPATION DERATING CURVE²
					vs
			FREE-AIR TEMPERATURE
1400
1200
1000
800
600				PWP Package
				RθJA = 178°C/W
400
200
0
25		50		75		100		125		150

TA ± Free-Air Temperature ± °C

Figure 3

PD ± Maximum Continuous Dissipation ± W

MAXIMUM CONTINUOUS DISSIPATION² vs

CASE TEMPERATURE

30

25

20

PWP Package

15

10

Measured with the exposed thermal pad coupled to an infinite heat sink with a

5thermally conductive compound (the

thermal conductivity of the compound is 0.815 W/m °C). The RθJC is 3.5°C/W.

0

25	50	75	100	125	150
		TC ± Case Temperature ± °C

Figure 4

²Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C.

For guidelines on maintaining junction temperature within recommended operating range, see the Thermal Information section.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q

LOW-DROPOUT VOLTAGE REGULATORS

SLVS152A ± NOVEMBER 1996 ± REVISED JANUARY 1997

recommended operating conditions

							MIN	MAX	UNIT
						TPS71H01Q	2.5	10
	Input voltage, VI²					TPS71H33Q	3.77	10	V
						TPS71H48Q	5.2	10
						TPS71H50Q	5.33	10
	High-level input voltage at		EN,		VIH		2		V
	Low-level input voltage at			VIL				0.5	V
		EN,
	Output current range, IO						0	500	mA
	Operating virtual junction temperature range, TJ						± 40	125	°C

²Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To

calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load) Because the TPS71H01 is programmable, rDS(on) should be used to calculate VDO before applying the above equation. The equation for calculating VDO from rDS(on) is given in Note 2 in the electrical characteristics table. The minimum value of 2.5 V is the absolute lower limit for the recommended input voltage range for the TPS71H01.

electrical characteristics at IO = 10 mA, EN = 0 V, CO = 4.7 μF/CSR³ = 1 Ω, SENSE/FB shorted to OUT

(unless otherwise noted)

TPS71H01Q, TPS71H33Q

PARAMETER

TEST CONDITIONS§

T

TPS71H48Q, TPS71H50Q

UNIT

J

MIN

TYP

MAX

25°C

285

350

Ground current (active mode)

EN ≤ 0.5 V,

VI = VO + 1 V,

μA

0 mA ≤ IO ≤ 500 mA

± 40°C to 125°C

460

Input current (standby mode)

= VI,

2.7 V ≤ VI

≤ 10 V

25°C

0.5

μA

EN

± 40°C to 125°C

2

Output current limit

VO = 0,

VI = 10 V

25°C

1.2

2

A

± 40°C to 125°C

2

Pass-element leakage current in standby

25°C

0.5

μA

EN = VI,

2.7 V ≤ VI

≤ 10 V

mode

°

°

1

± 40 C to 125 C

PG leakage current

Normal operation,

VPG = 10 V

25°C

0.02

0.5

μA

± 40°C to 125°C

0.5

Output voltage temperature coefficient

± 40°C to 125°C

61

75

ppm/°C

Thermal shutdown junction temperature

165

°C

2.5 V ≤ VI ≤ 6 V

±40°C to 125°C

2

V

EN logic high (standby mode)

6 V ≤ VI ≤ 10 V

2.7

logic low (active mode)

2.7 V ≤ VI ≤ 10 V

25°C

0.5

V

EN

± 40°C to 125°C

0.5

hysteresis voltage

25°C

50

mV

EN

input current

0 V ≤ VI ≤ 10 V

25°C

± 0.5

0.5

μA

EN

± 40°C to 125°C

± 0.5

0.5

Minimum VI for active pass element

25°C

2.05

2.5

V

± 40°C to 125°C

2.5

Minimum VI for valid PG

IPG = 300 μA

IPG = 300 μA

25°C

1.06

1.5

V

± 40°C to 125°C

1.9

³CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

§Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q

LOW-DROPOUT VOLTAGE REGULATORS

SLVS152A ± NOVEMBER 1996 ± REVISED JANUARY 1997

TPS71H01 electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, CO = 4.7 μF/CSR² = 1 Ω, FB shorted to OUT at device leads (unless otherwise noted)

PARAMETER		TEST CONDITIONS³			T	TPS71H01Q			UNIT
					J	MIN	TYP	MAX
Reference voltage (measured at		VI = 3.5 V,	IO = 10 mA		25°C		1.178		V
		2.5 V ≤ VI ≤ 10 V,	5 mA ≤ IO ≤ 500 mA,
FB with OUT connected to FB)				± 40°C to 125°C		1.143		1.213	V
		See Note 1
Reference voltage temperature				± 40°C to 125°C			61	75	ppm/°C
coefficient
		VI = 2.4 V,	50 μA ≤ IO ≤ 150 mA		25°C		0.7	1
				± 40°C to 125°C				1
		VI = 2.4 V,	150 mA ≤ IO ≤ 500 mA		25°C		0.83	1.3
Pass-element series resistance				± 40°C to 125°C				1.3
									Ω
(see Note 2)					°		0.52	0.85
		VI = 2.9 V,	50 μA ≤ IO ≤ 500 mA		25 C
				± 40°C to 125°C				0.85
		VI = 3.9 V,	50 μA ≤ IO ≤ 500 mA		25°C		0.32
		VI = 5.9 V,	50 μA ≤ IO ≤ 500 mA		25°C		0.23
Input regulation		VI = 2.5 V to 10 V,	50 μA ≤ IO ≤ 500 mA,		25°C			18	mV
		See Note 1		°	°			25
				± 40 C to 125 C
		IO = 5 mA to 500 mA,	2.5 V ≤ VI ≤ 10 V,		25°C			14	mV
		See Note 1		°	°			25
Output regulation				± 40 C to 125 C
		IO = 50 μA to 500 mA,	2.5 V ≤ VI ≤ 10 V,		25°C			22	mV
		See Note 1		°	°			54
				± 40 C to 125 C
			IO = 50 μA		25°C	48	59
Ripple rejection		f = 120 Hz		± 40°C to 125°C		44			dB
			IO = 500 mA,		25°C	45	54
			See Note 1	°	°	44
				± 40 C to 125 C
					25°C
Output noise-spectral density		f = 120 Hz					2		μV/√	Hz
		10 Hz ≤ f ≤ 100 kHz,	CO = 4.7 μF		25°C		95
Output noise voltage			CO = 10 μF		25°C		89		μVrms
		CSR² = 1 Ω
			CO = 100 μF		25°C		74
PG trip-threshold voltage	§	VFB voltage decreasing from above VPG		°	°	1.101		1.145	V
				± 40 C to 125 C
§		Measured at VFB			°		12		mV
PG hysteresis voltage					25 C
PG output low voltage§		I = 400 μA,	V = 2.13 V		25°C		0.1	0.4	V
		PG	I	± 40°C to 125°C				0.4
FB input current					25°C	± 10	0.1	10	nA
				± 40°C to 125°C		± 20		20

²CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

§ Output voltage programmed to 2.5 V with closed-loop configuration (see application information).

NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 27) to a point such that the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range.

2. To calculate dropout voltage, use equation:

VDO = IO rDS(on)

rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and

5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. (For other programmed values, see Figure 26.)

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7

TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q

LOW-DROPOUT VOLTAGE REGULATORS

SLVS152A ± NOVEMBER 1996 ± REVISED JANUARY 1997

TPS71H33 electrical characteristics at IO = 10 mA, VI = 4.3 V, EN = 0 V, CO = 4.7 μF/CSR² = 1 Ω, SENSE shorted to OUT (unless otherwise noted)

PARAMETER	TEST CONDITIONS³			T		TPS71H33Q		UNIT
				J	MIN	TYP	MAX
Output voltage	VI = 4.3 V,	IO = 10 mA		25°C		3.3		V
	4.3 V ≤ VI ≤ 10 V,	5 mA ≤ IO ≤ 500 mA	± 40°C to 125°C		3.23		3.37
	IO = 10 mA,	VI = 3.23 V		25°C		4.5	7
			± 40°C to 125°C				8
Dropout voltage	IO = 100 mA,	VI = 3.23 V		25°C		47	60	mV
			± 40°C to 125°C				80
	IO = 500 mA,	VI = 3.23 V		25°C		235	300
			± 40°C to 125°C				400
Pass-element series	(3.23 V ± VO)/IO,	VI = 3.23 V,		25°C		0.47	0.6
								Ω
resistance	I = 500 mA		°	°			0.8
	O		± 40 C to 125 C
Input regulation	VI = 4.3 V to 10 V,	50 μA ≤ IO ≤ 500 mA		25°C			20	mV
			± 40°C to 125°C				27
	IO = 5 mA to 500 mA,	4.3 V ≤ VI ≤ 10 V		25°C		21	38	mV
Output regulation			± 40°C to 125°C				75
	IO = 50 μA to 500 mA,	4.3 V ≤ VI ≤ 10 V		25°C		30	60	mV
			± 40°C to 125°C				120
		IO = 50 μA		25°C	43	54
Ripple rejection	f = 120 Hz		± 40°C to 125°C		40			dB
		IO = 500 mA		25°C	39	49
			± 40°C to 125°C		36
				25°C
Output noise-spectral density	f = 120 Hz					2		μV/√	Hz
	10 Hz ≤ f ≤ 100 kHz,	CO = 4.7 μF		25°C		274
Output noise voltage		CO = 10 μF		25°C		228		μVrms
	CSR² = 1 Ω
		CO = 100 μF		25°C		159
PG trip-threshold voltage	VO voltage decreasing from above VPG		± 40°C to 125°C		2.868		3	V
PG hysteresis voltage				25°C		35		mV
PG output low voltage	IPG = 1 mA,	VI = 2.8 V		25°C		0.22	0.4	V
			± 40°C to 125°C				0.4

²CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q

LOW-DROPOUT VOLTAGE REGULATORS

SLVS152A ± NOVEMBER 1996 ± REVISED JANUARY 1997

TPS71H48 electrical characteristics at IO = 10 mA, VI = 5.85 V, EN = 0 V, CO = 4.7 μF/CSR² = 1 Ω,

SENSE shorted to OUT (unless otherwise noted)

PARAMETER	TEST CONDITIONS³			T		TPS71H48Q		UNIT
				J	MIN	TYP	MAX
Output voltage	VI = 5.85 V,	IO = 10 mA		25°C		4.85		V
	5.85 V ≤ VI ≤ 10 V,	5 mA ≤ IO ≤ 500 mA	± 40°C to 125°C		4.75		4.95
	IO = 10 mA,	VI = 4.75 V		25°C		2.9	6
			± 40°C to 125°C				8
Dropout voltage	IO = 100 mA,	VI = 4.75 V		25°C		30	37	mV
			± 40°C to 125°C				54
	IO = 500 mA,	VI = 4.75 V		25°C		150	180
			± 40°C to 125°C				250
Pass-element series	(4.75 V ± VO)/IO,	VI = 4.75 V,		25°C		0.32	0.35
								Ω
resistance	I = 500 mA		°	°			0.52
	O		± 40 C to 125 C
Input regulation	VI = 5.85 V to 10 V,	50 μA ≤ IO ≤ 500 mA		25°C			27	mV
			± 40°C to 125°C				37
	IO = 5 mA to 500 mA,	5.85 V ≤ VI ≤ 10 V		25°C		12	42	mV
Output regulation			± 40°C to 125°C				80
	IO = 50 μA to 500 mA,	5.85 V ≤ VI ≤ 10 V		25°C		42	60	mV
			± 40°C to 125°C				130
		IO = 50 μA		25°C	42	53
Ripple rejection	f = 120 Hz		± 40°C to 125°C		39			dB
		IO = 500 mA		25°C	39	50
			± 40°C to 125°C		35
Output noise-spectral density	f = 120 Hz			25°C		2		μV/√	Hz
	10 Hz ≤ f ≤ 100 kHz,	CO = 4.7 μF		25°C		410
Output noise voltage		CO = 10 μF		25°C		328		μVrms
	CSR² = 1 Ω
		CO = 100 μF		25°C		212
PG trip-threshold voltage	VO voltage decreasing from above VPG		± 40°C to 125°C		4.5		4.7	V
PG hysteresis voltage				25°C		50		mV
PG output low voltage	IPG = 1.2 mA,	VI = 4.12 V		25°C		0.2	0.4	V
			± 40°C to 125°C				0.4

²CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

9

TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q

LOW-DROPOUT VOLTAGE REGULATORS

SLVS152A ± NOVEMBER 1996 ± REVISED JANUARY 1997

TPS71H50 electrical characteristics at IO = 10 mA, VI = 6 V, EN = 0 V, CO = 4.7 μF/CSR² = 1 Ω, SENSE shorted to OUT (unless otherwise noted)

PARAMETER	TEST CONDITIONS³			T	TPS71H50Q			UNIT
				J	MIN	TYP	MAX
Output voltage	VI = 6 V,	IO = 10 mA		25°C		5		V
	6 V ≤ VI ≤ 10 V,	5 mA ≤ IO ≤ 500 mA	± 40°C to 125°C		4.9		5.1
	IO = 10 mA,	VI = 4.88 V		25°C		2.9	6
			± 40°C to 125°C				8
Dropout voltage	IO = 100 mA,	VI = 4.88 V		25°C		27	32	mV
			± 40°C to 125°C				47
	IO = 500 mA,	VI = 4.88 V		25°C		146	170
			± 40°C to 125°C				230
Pass-element series	(4.88 V ± VO)/IO,	VI = 4.88 V.		25°C		0.29	0.32
								Ω
resistance	I = 500 mA		°	°			0.47
	O		± 40 C to 125 C
Input regulation	VI = 6 V to 10 V,	50 μA ≤ IO ≤ 500 mA		25°C			25	mV
			± 40°C to 125°C				32
	IO = 5 mA to 500 mA,	6 V ≤ VI ≤ 10 V		25°C		30	45	mV
Output regulation			± 40°C to 125°C				86
	IO = 50 μA to 500 mA,	6 V ≤ VI ≤ 10 V		25°C		45	65	mV
			± 40°C to 125°C				140
		IO = 50 μA		25°C	45	55
Ripple rejection	f = 120 Hz		± 40°C to 125°C		40			dB
		IO = 500 mA		25°C	42	52
			± 40°C to 125°C		36
				25°C
Output noise-spectral density	f = 120 Hz					2		μV/√	Hz
	10 Hz ≤ f ≤ 100 kHz,	CO = 4.7 μF		25°C		430
Output noise voltage		CO = 10 μF		25°C		345		μVrms
	CSR² = 1 Ω
		CO = 100 μF		25°C		220
PG trip-threshold voltage	VO voltage decreasing from above VPG		± 40°C to 125°C		4.55		4.75	V
PG hysteresis voltage				25°C		53		mV
PG output low voltage	IPG = 1.2 mA,	VI = 4.25 V		25°C		0.2	0.4	V
			± 40°C to 125°C				0.4

²CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

10	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q

LOW-DROPOUT VOLTAGE REGULATORS

SLVS152A ± NOVEMBER 1996 ± REVISED JANUARY 1997

TYPICAL CHARACTERISTICS

Table of Graphs

								FIGURE
							vs Output current	5
	IQ	Quiescent current
							vs Input voltage	6
							vs Free-air temperature	7
	VDO	Typical dropout voltage					vs Output current	8
	VDO	Change in dropout voltage					vs Free-air temperature	9
	VO	Change in output voltage					vs Free-air temperature	10
	VO	Output voltage					vs Input voltage	11
	VO	Change in output voltage					vs Input voltage	12
								13
	VO	Output voltage					vs Output current	14
								15
								16
								17
		Ripple rejection					vs Frequency	18
								19
								20
								21
		Output spectral noise density					vs Frequency	22
								23
								24
	rDS(on)	Pass-element resistance					vs Input voltage	25
	R	Divider resistance					vs Free-air temperature	26
	II(SENSE)	SENSE current					vs Free-air temperature	27
		FB leakage current					vs Free-air temperature	28
	VI	Minimum input voltage for active-pass element					vs Free-air temperature	29
		Minimum input voltage for valid PG					vs Free-air temperature	30
	II(EN)	Input current	(EN)				vs Free-air temperature	31
		Output voltage response from Enable						32
					(EN)
	VPG	Power-good (PG) voltage					vs Output voltage	33
	CSR	Compensation series resistance					vs Output current	34
								35
	CSR	Compensation series resistance					vs Ceramic capacitance	36
								37
	CSR	Compensation series resistance					vs Output current	38
								39
	CSR	Compensation series resistance					vs Ceramic capacitance	40
								41

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

11

TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q LOW-DROPOUT VOLTAGE REGULATORS

SLVS152A ± NOVEMBER 1996 ± REVISED JANUARY 1997

IQ ± Quiescent Current ± μ A

TYPICAL CHARACTERISTICS

QUIESCENT CURRENT	QUIESCENT CURRENT
vs	vs
OUTPUT CURRENT	INPUT VOLTAGE

355

TA = 25°C

345

335 TPS71Hxx, VI = 10 V

325

315

305

295 TPS71H50, VI = 6 V

285
			TPS71H48, VI = 5.85 V
275
		TPS71H33, V = 4.3 V
							I
265
	0		50		100		150		200			250	300	350	400	450	500

IO ± Output Current ± mA

	400	TA = 25°C
	350	RL = 10 Ω
μ A	300		TPS71H33
±									TPS71H48
Current
	250						TPS71H50
± Quiescent	200
						TPS71H01 With VO
	150					Programmed to 2.5 V
Q	100
I
	50
	0
	0	1	2	3	4	5	6	7	8	9	10
				VI ± Input Voltage ± V

Figure 5

Figure 6

IQ ± Quiesent Current ± μ A

TPS71H48Q

QUIESCENT CURRENT vs

FREE-AIR TEMPERATURE

400

VI = VO(nom) + 1 V

IO = 10 mA

350

300

250

200

150
±	50 ± 25		0	25	50	75	100	125
			TA ± Free-Air Temperature ± °C

Figure 7

Dropout Voltage ± V

DROPOUT VOLTAGE vs

OUTPUT CURRENT

0.3

TA = 25°C

0.25

TPS71H33

0.2

0.15

TPS71H48

0.1

TPS71H50

0.05

0

0	50	100	150	200	250	300	350	400	450	500
			IO ± Output Current ± mA

Figure 8

12	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265