TEXAS INSTRUMENTS TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q Technical data

SENSE ± Fixed voltage options only

(TPS7325, TPS7330, TPS7333, TPS7348, and TPS7350)

FB ± Adjustable version only (TPS7301)

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F ± JUNE 1995 ± REVISED JANUARY 1999

D Available in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V		D OR P PACKAGE
Fixed-Output and Adjustable Versions				(TOP VIEW)
D Integrated Precision Supply-Voltage
	GND				1	8			RESET
Supervisor Monitoring Regulator Output
									SENSE² /FB³
Voltage		EN			2	7
		IN			3	6			OUT
D Active-Low Reset Signal with 200-ms Pulse
		IN			4	5			OUT
Width

DVery Low Dropout Voltage . . . Maximum of 35 mV at IO = 100 mA (TPS7350)

DLow Quiescent Current ± Independent of Load . . . 340 A Typ

DExtremely Low Sleep-State Current,

0.5A Max

D2% Tolerance Over Full Range of Load,

Line, and Temperature for Fixed-Output Versions§

DOutput Current Range of 0 mA to 500 mA

DTSSOP Package Option Offers Reduced Component Height For Critical Applications

description

PW PACKAGE (TOP VIEW)

GND				1	20		RESET
GND				2	19		NC
GND				3	18		NC
NC				4	17		FB³
NC				5	16		NC
				6	15		SENSE²
	EN
NC				7	14		OUT
	IN			8	13		OUT
	IN			9	12		NC
	IN			10	11		NC

NC ± No internal connection

²

The TPS73xx devices are members of a family of

³

micropower low-dropout (LDO) voltage regulators.

They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.¶

AVAILABLE OPTIONS

OUTPUT VOLTAGE

NEGATIVE-GOING

RESET

PACKAGED DEVICES

(V)

THRESHOLD VOLTAGE (V)

CHIP FORM

TJ

SMALL

PLASTIC DIP

TSSOP

(Y)

MIN

TYP

MAX

MIN

TYP

MAX

OUTLINE

(P)

(PW)

(D)

4.9

5

5.1

4.55

4.65

4.75

TPS7350QD

TPS7350QP

TPS7350QPW

TPS7350Y

4.75

4.85

4.95

4.5

4.6

4.7

TPS7348QD

TPS7348QP

TPS7348QPW

TPS7348Y

±40°C to

3.23

3.3

3.37

2.868

2.934

3

TPS7333QD

TPS7333QP

TPS7333QPW

TPS7333Y

2.94

3

3.06

2.58

2.64

2.7

TPS7330QD

TPS7330QP

TPS7330QPW

TPS7330Y

125°C

2.425

2.5

2.575

2.23

2.32

2.39

TPS7325QD

TPS7325QP

TPS7325QPW

TPS7325Y

Adjustable

1.101

1.123

1.145

TPS7301QD

TPS7301QP

TPS7301QPW

TPS7301Y

1.2 V to 9.75 V

The D and PW packages are available taped and reeled. Add an R suffix to device type (e.g., TPS7350QDR). The TPS7301Q is programmable using an external resistor divider (see application information). The chip form is tested at 25°C.

§ The TPS7325 has a tolerance of ± 3% over the full temperature range.

¶The TPS71xx and the TPS72xx are 500-mA and 250-mA output regulators respectively, offering performance similar to that of the TPS73xx but without the delayed-reset function. The TPS72xx devices are further differentiated by availability in 8-pin thin-shrink small-outline packages (TSSOP) for applications requiring minimum package size.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1999, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F ± JUNE 1995 ± REVISED JANUARY 1999

description (continued)

The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.

If that occurs, the RESET output (open-drain NMOS) turns on, taking the RESET signal low. RESET stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET goes high.

An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35 mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure 1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 A over the full range of output current, 0 mA to 500 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.

The LDO family also features a sleep mode; applying a logic high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 0.5 A maximum at TJ = 25°C.

The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2 mm.

	0.3
		TA = 25°C							TPS7330
	0.25
								TPS7333
± V	0.2					TPS7325
Voltage
	0.15
Dropout								TPS7348
	0.1
								TPS7350
	0.05
	0
	0	50	100	150	200	250	300	350	400	450	500
				IO ± Output Current ± mA

	TPS73xxPW²
VI	8		20		To System
	IN	RESET			Reset
	9		15
				250 kΩ
	IN	SENSE
	10		14		VO
	IN		OUT
0.1 µF	6		13
	EN		OUT		CO³
				+
		GND		10	µF
	1	2	3	CSR = 1 Ω

² TPS7325, TPS7330, TPS7333, TPS7348, TPS7350 (fixed-voltage

options)

³Capacitor selection is nontrivial. See application information section for details.

Figure 1. Dropout Voltage Versus Output Current

Figure 2. Typical Application Configuration

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F ± JUNE 1995 ± REVISED JANUARY 1999

TPS73xxY chip information

These chips, when properly assembled, display characteristics similar to those of the TPS73xxQ. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

(5)

(4)

(6)

(7)

80

(1)

(2)

(3)

92

					(5)
			(3)		SENSE²
	IN				(6)
				TPS73xx	FB³
			(2)		(4)
	EN				OUT
					(7)
					RESET

(1) GND

CHIP THICKNESS: 15 TYPICAL

BONDING PADS: 4 × 4 MINIMUM

TJmax = 150°C

TOLERANCES ARE ± 10%.

ALL DIMENSIONS ARE IN MILS.

² SENSE ± Fixed voltage options only (TPS7325, TPS7330, TPS7333, TPS7348, and TPS7350)

³ FB ± Adjustable version only (TPS7301)

NOTE A. For most applications, OUT and SENSE should be tied together as close as possible to the device; for other implementations, refer to SENSE-pin connection discussion in the applications information section of this data sheet.

functional block diagram
IN					RESISTOR DIVIDER OPTIONS
EN	¶		¶	¶	DEVICE	R1	R2	UNIT
							∞	Ω
					TPS7301	0
				RESET	TPS7325	260	233	kΩ
					TPS7330	358	233	kΩ
	_				TPS7333	420	233	kΩ
	+				TPS7348	726	233	kΩ
				OUT	TPS7350	756	233	kΩ
					NOTE A. Resistors are nominal values only.
		+	Delayed	SENSE§/FB
Vref		_	Reset	R1
						COMPONENT COUNT
						MOS transistors		464
				R2		Bilpolar transistors		41
						Diodes		4
						Capacitors		17
						Resistors		76

GND

§ For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to SENSE-pin connection discussion in applications information section.

¶ Switch positions are shown with EN low (active).

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F ± JUNE 1995 ± REVISED JANUARY 1999

timing diagram

VI
Vres²			Vres
			t
VO	V	V	IT +
	IT +
Threshold
Voltage
	VIT ±		VIT ±
			t
RESET	200 ms		200 ms
Output
	Delay		Delay
Output			Output
Undefined			Undefined
			t

²Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³

Input voltage range§, V ,	RESET, SENSE, EN . . . . . . . . . . . . . . . . . . . .				. . . . . . . . . . . . . . . . . . . . ±0.3 V to 11	V
I
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2	A
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					See Dissipation Rating Tables 1 and 2
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . ±55°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . ±65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . .					. . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

§ All voltage values are with respect to network terminal ground.

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F ± JUNE 1995 ± REVISED JANUARY 1999

DISSIPATION RATING TABLE 1 ± FREE-AIR TEMPERATURE (SEE FIGURE 3)

	PACKAGE	TA ≤ 25°C	DERATING FACTOR	TA = 70°C	TA = 125°C
		POWER RATING	ABOVE TA = 25°C	POWER RATING	POWER RATING
	D	725 mW	5.8 mW/°C	464 mW	145 mW
	P	1175 mW	9.4 mW/°C	752 mW	235 mW
	PW²	700 mW	5.6 mW/°C	448 mW	140 mW
		DISSIPATION RATING TABLE 2 ± CASE TEMPERATURE (SEE FIGURE 4)
	PACKAGE	TC ≤ 25°C	DERATING FACTOR	TC = 70°C	TC = 125°C
		POWER RATING	ABOVE TC = 25°C	POWER RATING	POWER RATING
	D	2188 mW	9.4 mW/°C	1765 mW	1248 mW
	P	2738 mW	21.9 mW/°C	1752 mW	548 mW
	PW²	4025 mW	32.2 mW/°C	2576 mW	805 mW

²Refer to Thermal Information section for detailed power dissipation considerations when using the TSSOP package.

MAXIMUM CONTINUOUS DISSIPATION	MAXIMUM CONTINUOUS DISSIPATION
vs	vs
FREE-AIR TEMPERATURE	CASE TEMPERATURE

	1400							4800
							± mW
±mW								4400
	1200							4000
Dissipation							Dissipation
								3600
	1000		P Package					3200
			RθJA = 106°C/W					2800
Continuous	800						Continuous
								2400
	600				D Package			2000
					RθJA = 172°C/W
								1600
± Maximum							± Maximum
	400	PW Package						1200
	200	RθJA = 178°C/W						800
D							D	400
P							P
	0				125	150		0
	25	50	75	100
		TA ± Free-Air Temperature ± °C

PW Package

RθJC = 37°C/W

P Package

RθJC = 46°C/W

D Package

RθJC = 57°C/W

25	50	75	100	125	150
		TC ± Case Temperature ± °C

Figure 3

Figure 4

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F ± JUNE 1995 ± REVISED JANUARY 1999

recommended operating conditions

						MIN	MAX	UNIT
					TPS7301Q	2.47	10	V
					TPS7325Q	3.1	10
Input voltage, VI²					TPS7330Q	3.5	10	V
					TPS7333Q	3.77	10
								V
					TPS7348Q	5.2	10
					TPS7350Q	5.33	10
High-level input voltage at		EN,		VIH		2		V
Low-level input voltage at			VIL				0.5	V
	EN,
Output current range, IO						0	500	mA
Operating virtual junction temperature range, TJ						± 40	125	°C

²Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage, VDO, at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To calculate the minimum input voltage for the maximum load current used in a given application, use the following equation:

VI(min) + VO(max) )VDO(max load)

Becausethe TPS7301 is programmable, rDS(on) should be used to calculate VDO before applyingthe aboveequation.Theequationforcalculating VDO from rDS(on) is given in Note 2 in the TPS7301 electrical characteristics table. The minimum value of 2.97 V is the absolute lower limit for the recommended input voltage range for the TPS7301.

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F ± JUNE 1995 ± REVISED JANUARY 1999

electrical characteristics at IO = 10 mA, EN = 0 V, Co = 4.7 µF (CSR³ = 1 Ω), SENSE/FB shorted to

OUT (unless otherwise noted)

PARAMETER

TEST CONDITIONS§

T

MIN

TYP

MAX

UNIT

J

25°C

340

400

Ground current (active mode)

EN ≤ 0.5 V,

VI = VO + 1 V,

A

0 mA ≤ IO ≤ 500 mA

± 40°C to 125°C

550

Input current (standby mode)

= VI,

2.7 V ≤ VI ≤ 10 V

25°C

0.01

0.5

A

EN

± 40°C to 125°C

2

Output current limit

VO = 0 V,

VI = 10 V

25°C

1.2

2

A

± 40°C to 125°C

2

Pass-element leakage current in standby

25°C

0.01

0.5

A

EN = VI,

2.7 V ≤ VI ≤ 10 V

mode

°

°

1

± 40 C to 125 C

leakage current

Normal operation,

V at

= 10 V

25°C

0.02

0.5

A

RESET

RESET

± 40°C to 125°C

0.5

Output voltage temperature coefficient

± 40°C to 125°C

61

75

ppm/°C

Thermal shutdown junction temperature

165

°C

logic high (standby mode)

2.5 V ≤ VI ≤ 6 V

±40°C to 125°C

2

V

EN

6 V ≤ VI ≤ 10 V

2.7

logic low (active mode)

2.7 V ≤ VI ≤ 10 V

25°C

0.5

V

EN

± 40°C to 125°C

0.5

hysteresis voltage

25°C

50

mV

EN

input current

0 V ≤ VI ≤ 10 V

25°C

± 0.5

0.001

0.5

A

EN

± 40°C to 125°C

± 0.5

0.5

Minimum VI for active pass element

25°C

2.05

2.5

V

± 40°C to 125°C

2.5

IO(RESET) = ±300 A

25°C

1

1.5

V

Minimum VI for valid RESET

± 40°C to 125°C

1.9

³CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

§Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

7

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F ± JUNE 1995 ± REVISED JANUARY 1999

TPS7301Q electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, Co = 4.7 µF (CSR² = 1 Ω), FB shorted to OUT at device leads (unless otherwise noted)

PARAMETER

TEST CONDITIONS³

T

MIN

TYP

MAX

UNIT

J

25°C

1.182

V

Reference voltage (measured at FB)

2.5 V ≤ VI ≤ 10 V,

5 mA ≤ IO ≤ 500 mA,

± 40°C to 125°C

1.147

1.217

V

See Note 1

Reference voltage temperature

± 40°C to 125°C

61

75

ppm/°C

coefficient

VI = 2.4 V,

50 A ≤ IO

≤ 150 mA

25°C

0.7

1

± 40°C to 125°C

1

VI = 2.4 V,

150 mA ≤ IO ≤ 500 mA

25°C

0.83

1.3

Pass-element series resistance

± 40°C to 125°C

1.3

Ω

(See Note 2)

°

0.52

0.85

VI = 2.9 V,

50 A ≤ IO

≤ 500 mA

25 C

± 40°C to 125°C

0.85

VI = 3.9 V,

50 A ≤ IO ≤ 500 mA

25°C

0.32

VI = 5.9 V,

50 A ≤ IO ≤ 500 mA

25°C

0.23

Input regulation

VI = 2.5 V to 10 V,

50 A ≤ IO ≤ 500 mA,

25°C

3

18

mV

See Note 1

°

°

25

± 40 C to 125 C

2.5 V ≤ VI ≤ 10 V,

IO = 5 mA to 500 mA,

25°C

5

14

mV

See Note 1

°

°

25

Output regulation

± 40 C to 125 C

2.5 V ≤ VI ≤ 10 V,

IO = 50 A to 500 mA,

25°C

7

22

mV

See Note 1

°

°

54

± 40 C to 125 C

IO = 50 A

25°C

48

59

Ripple rejection

f = 120 Hz

± 40°C to 125°C

44

dB

IO = 500 mA,

25°C

45

54

See Note 1

°

°

44

± 40 C to 125 C

25°C

Output noise-spectral density

f = 120 Hz

2

V/√

Hz

Co = 4.7 F

25°C

95

Output noise voltage

10 Hz ≤ f ≤ 100 kHz

Co = 10 F

25°C

89

Vrms

Co = 100 F

25°C

74

§

VO(FB) decreasing

°

°

1.101

1.145

V

RESET trip-threshold voltage

± 40 C to 125 C

§

Measured at VO(FB)

°

12

mV

RESET hysteresis voltage

25 C

output low voltage§

V

= 2.13 V,

I

= 400 A

25°C

0.1

0.4

V

RESET

I

O(RESET)

± 40°C to 125°C

0.4

FB input current

25°C

± 10

0.1

10

nA

± 40°C to 125°C

± 20

20

²CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

§ Output voltage programmed to 2.5 V with closed-loop configuration (see application information).

NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 33) to a point where the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range.

2.To calculate dropout voltage, use equation: VDO = IO rDS(on)

rDS(on) is a function of both output current and input voltage. This parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively. For other

programmed values, refer to Figure 33.

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F ± JUNE 1995 ± REVISED JANUARY 1999

TPS7325Q electrical characteristics at I = 10 mA, V

= 3.5 V,

= 0 V, C

= 10 µF (CSR² = 1 Ω), SENSE

EN

o

O

I

shorted to OUT (unless otherwise noted)

PARAMETER

TEST CONDITIONS³

T

MIN

TYP

MAX

UNIT

J

Output voltage

25°C

2.45

2.5

2.55

V

3.5 V ≤ VI ≤ 10 V,

5 mA ≤ IO ≤ 500 mA

± 40°C to 125°C

2.425

2.575

IO = 10 mA,

VI = 2.97 V

25°C

5

± 40°C to 125°C

14

Dropout voltage§

I = 100 mA,

V = 2.97 V

25°C

50

80

mV

O

I

± 40°C to 125°C

150

IO = 500 mA,

VI = 2.97 V

25°C

270

400

± 40°C to 125°C

600

Pass-element series resistance

§

(2.97 V ± VO)/IO,

VI = 2.97 V,

25°C

0.5

0.7

Ω

I = 500 mA

°

°

1.4

O

± 40 C to 125 C

Input regulation

VI = 3.5 V to 10 V,

50 A ≤ IO ≤ 500 mA

25°C

6

20

mV

± 40°C to 125°C

25

IO = 5 mA to 500 mA,

3.5 V ≤ VI ≤ 10 V

25°C

20

32

mV

Output regulation

± 40°C to 125°C

50

IO = 50 A to 500 mA,

3.5 V ≤ VI ≤ 10 V

25°C

28

60

mV

± 40°C to 125°C

100

IO = 50 A

25°C

50

53

Ripple rejection

f = 120 Hz

± 40°C to 125°C

49

dB

IO = 500 mA

25°C

49

53

± 40°C to 125°C

32

25°C

Output noise-spectral density

f = 120 Hz

2

V/√

Hz

Co = 4.7 F

25°C

274

Output noise voltage

10 Hz ≤ f ≤ 100 kHz

Co = 10 F

25°C

228

Vrms

Co = 100 F

25°C

159

VO decreasing

± 40°C to 125°C

2.23

2.32

2.39

V

RESET

trip-threshold voltage

25°C

0.14

0.4

RESET output low voltage

VI = 2.1 V,

IO(RESET) = ±0.8 mA

V

± 40°C to 125°C

0.4

² CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

§Dropout test and pass-element series resistance test are not production tested. Test method requires SENSE terminal to be disconnected from output voltage.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

9

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F ± JUNE 1995 ± REVISED JANUARY 1999

TPS7330Q electrical characteristics at IO = 10 mA, VI = 4 V, EN = 0 V, Co = 4.7 µF (CSR² = 1 Ω), SENSE shorted to OUT (unless otherwise noted)

PARAMETER

TEST CONDITIONS³

T

MIN

TYP

MAX

UNIT

J

Output voltage

25°C

3

V

4 V ≤ VI ≤ 10 V,

5 mA ≤ IO ≤ 500 mA

± 40°C to 125°C

2.94

3.06

IO = 10 mA,

VI = 2.94 V

25°C

5.2

7

± 40°C to 125°C

10

Dropout voltage

IO = 100 mA,

VI = 2.94 V

25°C

52

75

mV

± 40°C to 125°C

100

IO = 500 mA,

VI = 2.94 V

25°C

267

450

± 40°C to 125°C

500

Pass-element series resistance

(2.94 V ± VO)/IO,

VI = 2.94 V,

25°C

0.5

0.7

Ω

I = 500 mA

°

°

1

O

± 40 C to 125 C

Input regulation

VI = 4 V to 10 V,

50 A ≤ IO ≤ 500 mA

25°C

6

23

mV

± 40°C to 125°C

29

IO = 5 mA to 500 mA,

4 V ≤ VI ≤ 10 V

25°C

20

32

mV

Output regulation

± 40°C to 125°C

60

IO = 50 A to 500 mA,

4 V ≤ VI ≤ 10 V

25°C

28

60

mV

± 40°C to 125°C

120

IO = 50 A

25°C

43

53

Ripple rejection

f = 120 Hz

± 40°C to 125°C

40

dB

IO = 500 mA

25°C

39

53

± 40°C to 125°C

36

25°C

Output noise-spectral density

f = 120 Hz

2

V/√

Hz

Co = 4.7 F

25°C

274

Output noise voltage

10 Hz ≤ f ≤ 100 kHz

Co = 10 F

25°C

228

Vrms

Co = 100 F

25°C

159

VO decreasing

± 40°C to 125°C

2.58

2.64

2.7

V

RESET

trip-threshold voltage

25°C

0.14

0.4

RESET output low voltage

VI = 2.6 V,

IO(RESET) = ±0.8 mA

V

± 40°C to 125°C

0.4

²CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

10	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F ± JUNE 1995 ± REVISED JANUARY 1999

TPS7333Q electrical characteristics at IO = 10 mA, VI = 4.3 V, EN = 0 V, Co = 4.7 µF (CSR² = 1 Ω),

SENSE shorted to OUT (unless otherwise noted)

PARAMETER

TEST CONDITIONS³

T

MIN

TYP

MAX

UNIT

J

Output voltage

25°C

3.3

V

4.3 V ≤ VI ≤ 10 V,

5 mA ≤ IO ≤ 500 mA

± 40°C to 125°C

3.23

3.37

IO = 10 mA,

VI = 3.23 V

25°C

4.5

7

± 40°C to 125°C

8

Dropout voltage

IO = 100 mA,

VI = 3.23 V

25°C

44

60

mV

± 40°C to 125°C

80

IO = 500 mA,

VI = 3.23 V

25°C

235

300

± 40°C to 125°C

400

Pass-element series resistance

(3.23 V ± VO)/IO,

VI = 3.23 V,

25°C

0.44

0.6

Ω

I = 500 mA

°

°

0.8

O

± 40 C to 125 C

Input regulation

VI = 4.3 V to 10 V,

50 A ≤ IO ≤ 500 mA

25°C

6

23

mV

± 40°C to 125°C

29

IO = 5 mA to 500 mA,

4.3 V ≤ VI ≤ 10 V

25°C

21

38

mV

Output regulation

± 40°C to 125°C

75

IO = 50 A to 500 mA, 4.3 V ≤ VI ≤ 10 V

25°C

31

60

mV

± 40°C to 125°C

120

IO = 50 A

25°C

43

51

Ripple rejection

f = 120 Hz

± 40°C to 125°C

40

dB

IO = 500 mA

25°C

39

49

± 40°C to 125°C

36

25°C

Output noise-spectral density

f = 120 Hz

2

V/√

Hz

Co = 4.7 F

25°C

274

Output noise voltage

10 Hz ≤ f ≤ 100 kHz

Co = 10 F

25°C

228

Vrms

Co = 100 F

25°C

159

trip-threshold voltage

VO decreasing

± 40°C to 125°C

2.868

V

RESET

hysteresis voltage

25°C

18

mV

RESET

25°C

0.17

0.4

RESET output low voltage

VI = 2.8 V,

IO(RESET) = ±1 mA

V

± 40°C to 125°C

0.4

²CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

11

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F ± JUNE 1995 ± REVISED JANUARY 1999

TPS7348Q electrical characteristics at IO = 10 mA, VI = 5.85 V, EN = 0 V, Co = 4.7 µF (CSR² = 1 Ω),

SENSE shorted to OUT (unless otherwise noted)

PARAMETER

TEST CONDITIONS³

T

MIN

TYP

MAX

UNIT

J

Output voltage

25°C

4.85

V

5.85 V ≤ VI ≤ 10 V,

5 mA ≤ IO ≤ 500 mA

± 40°C to 125°C

4.75

4.95

IO = 10 mA,

VI

= 4.75 V

25°C

2.9

6

± 40°C to 125°C

8

Dropout voltage

IO = 100 mA,

VI

= 4.75 V

25°C

28

37

mV

± 40°C to 125°C

54

IO = 500 mA,

VI

= 4.75 V

25°C

150

180

± 40°C to 125°C

250

Pass-element series resistance

(4.75 V ± VO)/IO,

VI = 4.75 V,

25°C

0.28

0.37

Ω

I = 500 mA

°

°

0.52

O

± 40 C to 125 C

Input regulation

VI = 5.85 V to 10 V,

50 A ≤ IO ≤ 500 mA

25°C

9

35

mV

± 40°C to 125°C

37

IO = 5 mA to 500 mA,

5.85 V ≤ VI ≤ 10 V

25°C

28

42

mV

Output regulation

± 40°C to 125°C

80

IO = 50 A to 500 mA, 5.85 V ≤ VI ≤ 10 V

25°C

42

65

mV

± 40°C to 125°C

130

IO

= 50 A

25°C

42

53

Ripple rejection

f = 120 Hz

± 40°C to 125°C

39

dB

IO

= 500 mA

25°C

39

50

± 40°C to 125°C

35

Output noise-spectral density

f = 120 Hz

25°C

2

V/√

Hz

Co = 4.7 F

25°C

410

Output noise voltage

10 Hz ≤ f ≤ 100 kHz

Co = 10 F

25°C

328

Vrms

Co = 100 F

25°C

212

trip-threshold voltage

VO decreasing

± 40°C to 125°C

4.5

4.7

V

RESET

hysteresis voltage

25°C

26

mV

RESET

25°C

0.2

0.4

RESET output low voltage

IO(RESET) = ±1.2 mA,VI

= 4.12 V

V

± 40°C to 125°C

0.4

²CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

12	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F ± JUNE 1995 ± REVISED JANUARY 1999

TPS7350Q electrical characteristics at IO = 10 mA, VI = 6 V, EN = 0 V, Co = 4.7 µF (CSR² = 1 Ω), SENSE shorted to OUT (unless otherwise noted)

PARAMETER

TEST CONDITIONS³

T

MIN

TYP

MAX

UNIT

J

Output voltage

25°C

5

V

6 V ≤ VI ≤ 10 V,

5 mA ≤ IO ≤ 500 mA

± 40°C to 125°C

4.9

5.1

IO = 10 mA,

VI = 4.88 V

25°C

2.9

6

± 40°C to 125°C

8

Dropout voltage

IO = 100 mA,

VI = 4.88 V

25°C

27

35

mV

± 40°C to 125°C

50

IO = 500 mA,

VI = 4.88 V

25°C

146

170

± 40°C to 125°C

230

Pass-element series resistance

(4.88 V ± VO)/IO,

VI = 4.88 V,

25°C

0.27

0.35

Ω

I = 500 mA

°

°

0.5

O

± 40 C to 125 C

Input regulation

VI = 6 V to 10 V,

50 A ≤ IO ≤ 500 mA

25°C

4

25

mV

± 40°C to 125°C

45

IO = 5 mA to 500 mA,

6 V ≤ VI ≤ 10 V

25°C

30

45

mV

Output regulation

± 40°C to 125°C

86

IO = 50 A to 500 mA,

6 V ≤ VI ≤ 10 V

25°C

45

65

mV

± 40°C to 125°C

140

IO = 50 A

25°C

43

53

Ripple rejection

f = 120 Hz

± 40°C to 125°C

38

dB

IO = 500 mA

25°C

41

51

± 40°C to 125°C

36

Output noise-spectral density

f = 120 Hz

25°C

2

V/√

Hz

Co = 4.7 F

25°C

430

Output noise voltage

10 Hz ≤ f ≤ 100 kHz

Co = 10 F

25°C

345

Vrms

Co = 100 F

25°C

220

trip-threshold voltage

VO decreasing

± 40°C to 125°C

4.55

4.75

V

RESET

hysteresis voltage

25°C

28

mV

RESET

25°C

0.15

0.4

RESET output low voltage

IO(RESET) = ±1.2 mA,

VI = 4.25 V

V

± 40°C to 125°C

0.4

²CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

13

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F ± JUNE 1995 ± REVISED JANUARY 1999

switching characteristics

					TPS7301Q, TPS7333Q
		PARAMETER	TEST CONDITIONS	TJ	TPS7348Q, TPS7350Q			UNIT
					MIN	TYP	MAX
			See Figure 5	25°C	140	200	260	ms
	RESET time-out delay
				± 40°C to 125°C	100		300

electrical characteristics at I = 10 mA,

= 0 V, C

= 4.7 µF (CSR² = 1 Ω), T

= 25°C, SENSE/FB

EN

o

J

O

shorted to OUT (unless otherwise noted)

TPS7301Y, TPS7333Y

PARAMETER

TEST CONDITIONS³

TPS7348Y, TPS7350Y

UNIT

MIN

TYP MAX

≤ 0.5 V,

VI = VO + 1 V,

Ground current (active mode)

EN

340

A

0 mA ≤ IO ≤ 500 mA

Input current (standby mode)

= VI,

2.7 V ≤ VI ≤ 10 V

0.01

A

EN

Output current limit

VO = 0 V,

VI = 10 V

1.2

A

Pass-element leakage current in standby mode

= VI,

2.7 V ≤ VI ≤ 10 V

0.01

A

EN

leakage current

0.02

A

RESET

Normal operation,

V at

RESET

= 10 V

Thermal shutdown junction temperature

165

°C

logic low (active mode)

2.7 V ≤ VI ≤ 10 V

0.5

V

EN

hysteresis voltage

50

mV

EN

input current

0 V ≤ VI ≤ 10 V

0.001

A

EN

Minimum VI for active pass element

2.05

V

Minimum VI for valid

IO(RESET) = ± 300 A

1

V

RESET

²CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

14	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265