Texas Instruments TLV1578IDA, TLV1578IDAR, TLV1578EVM, TLV1578CDAR, TLV1571IDW Datasheet

TLV1571, TLV1578 2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C ±MARCH 1999 ± REVISED FEBRUARY 2000

features

DFast Throughput Rate: 1.25 MSPS at 5 V,

625 KSPS at 3 V

DWide Analog Input: 0 V to AVDD

DDifferential Nonlinearity Error: < ± 1 LSB

DIntegral Nonlinearity Error: < ± 1 LSB

D8-to-1 Analog MUX ± TLV1578

DInternal OSC

DSingle 2.7-V to 5.5-V Supply Operation

DLow Power: 12 mW at 3 V and 35 mW at 5 V

DAuto Power Down of 1 mA Max

DSoftware Power Down: 10 A Max

DHardware Configurable

DDSP and Microcontroller Compatible Parallel Interface

DBinary/Twos Complement Output

DHardware Controlled Extended Sampling

DChannel Sweep Mode Operation and Channel Select

DHardware or Software Start of Conversion

applications

DMass Storage and HDD

DAutomotive

DDigital Servos

DProcess Control

DGeneral-Purpose DSP

DImage Sensor Processing

description

TLV1578

DA PACKAGE (TOP VIEW)

	CH0						1	32					CH7
	CH1						2	31					CH6
	CH2						3	30					CH5
	CH3						4	29					CH4
		CS					5	28					MO
		WR					6	27					AIN
		RD					7	26					AVDD
	CLK						8	25					AGND
DGND							9	24					REFM
DVDD							10	23					REFP
							11
INT/EOC								22						CSTART
			D0				12	21					D9/A1
			D1				13	20					D8/A0
			D2				14	19					D7
			D3				15	18					D6
			D4				16	17					D5
								TLV1571
						DW OR PW PACKAGE
								(TOP VIEW)
														NC
			CS				1	24
														AIN
		WR					2	23
		RD					3	22						AVDD
	CLK						4	21						AGND
DGND							5	20						REFM
DVDD							6	19							REFP
INT/EOC							7	18							CSTART
			D0				8	17							D9/A1
			D1				9	16							D8/A0
			D2				10	15							D7
			D3				11	14							D6
			D4				12	13							D5

NC ± No internal connection

The TLV1571/1578 is a 10-bit data acquisition system that combines an 8-channel input multiplexer (MUX), a high-speed 10-bit ADC, and a parallel interface. The device contains two on-chip control registers allowing control of channel selection, software conversion start, and power down via the bidirectional parallel port. The control registers can be set to a default mode by applying a dummy RD signal when WR is tied low. This allows the TLV1571/1578 to be configured by hardware. The MUX is independently accessible. This allows the user to insert a signal conditioning circuit such as an antialiasing filter or an amplifier, if required, between the MUX and the ADC. Therefore, one signal conditioning circuit can be used for all eight channels. The TLV1571 is a single channel analog input device with all the same functions as the TLV1578.

The TLV1571/TLV1578 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range from 0 V to AVDD and digitizes the input at a maximum 1.25 MSPS throughput rate at 5 V. The power dissipations are only 12 mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode that automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the ADC is further powered down to only 10 A.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2000, Texas Instruments Incorporated

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1

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C ±MARCH 1999 ± REVISED FEBRUARY 2000

description (continued)

Very high throughput rate, simple parallel interface, and low power consumption make the TLV1571/TLV1578 an ideal choice for high-speed digital signal processing requiring multiple analog inputs.

AVAILABLE OPTIONS

		PACKAGE
TA
	32 TSSOP	24 SOP	24 TSSOP
	(DA)	(DW)	(PW)
0°C to 70°C	TLV1578CDA	TLV1571CDW	TLV1571CPW
± 40°C to 85°C	TLV1578IDA	TLV1571IDW	TLV1571IPW

functional block diagram ± TLV1571/78

MO AV	DD	AIN	REFP REFM	DVDD

CH0 ± CH7

CLK

MUX

TLV1578 Only

Internal
Clock	MUX

CS

RD

WR CSTART

		Three	D0 ± D7
	10-BIT
		State
	SAR ADC
		Latch	D8/A0
			D9/A1
	Input Registers		INT/EOC
	and Control Logic

AGND

DGND

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TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C ±MARCH 1999 ± REVISED FEBRUARY 2000

Terminal Functions

TERMINAL

NAME

NO.

I/O

DESCRIPTION

TLV1571

TLV1578

AGND

21

25

Analog ground

AIN

23

27

I

ADC analog input (used as single analog input channel for TLV1571)

AVDD

22

26

Analog supply voltage, 2.7 V to 5.5 V

CH0 ± CH7

±

1±4,

I

Analog input channels

29±32

CLK

4

8

I

External clock input

1

5

I

Chip select. A logic low on

enables the TLV1571/TLV1578.

CS

CS

18

22

I

Hardware sample and conversion start input. The falling edge of

starts sampling and

CSTART

CSTART

the rising edge of CSTART starts conversion.

DGND

5

9

Digital ground

DVDD

6

10

Digital supply voltage, 2.7 V to 5.5 V

D0 ± D7

8 ±12,

12±16,

I/O

Bidirectional 3-state data bus

13±15

17±19

D8/A0

16

20

I/O

Bidirectional 3-state data bus. D8/A0 along with D9/A1 is used as address lines to access CR0

and CR1 for initialization.

D9/A1

17

21

I/O

Bidirectional 3-state data bus. D9/A1 along with D8/A0 is used as address lines to access CR0

and CR1 for initialization.

7

11

O

End-of-conversion/interrupt

INT/EOC

MO

28

O

On-chip mux analog output

NC

24

Not connected

RD

3

7

I

Read data. A falling edge on

RD

enables a read operation on the data bus when

CS

is low.

REFM

20

24

I

Lower reference voltage (nominally ground). REFM must be supplied or REFM pin must be

grounded.

REFP

19

23

I

Upper reference voltage (nominally AVDD). The maximum input voltage range is determined by

the difference between the voltage applied to REFP and REFM.

2

6

I

Write data. A rising edge on the

latches in configuration data when

is low. When using

WR

WR

CS

software conversion start, a rising edge on

WR

also initiates an internal sampling start pulse.

When WR is tied to ground, the ADC in nonprogrammable (hardware configuration mode).

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3

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C ±MARCH 1999 ± REVISED FEBRUARY 2000

detailed description

Ain

								Charge
							Redistribution
								DAC
						_
								SAR		ADC Code
						+		Register
REFM
								Control
								Logic

Figure 1. Analog-to-Digital SAR Converter

The TLV1571/78 is a successive-approximation ADC utilizing a charge redistribution DAC. Figure 1 shows a simplified version of the ADC.

The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is balanced, the conversion is complete and the ADC output code is generated.

sampling frequency, fs

The TLV1571/TLV1578 requires 16 CLKs for each conversion, therefore the equivalent maximum sampling frequency achievable with a given CLK frequency is:

fs(max) = (1/16) fCLK

The TLV1571 and TLV1578 are software configurable. The first two MSB bits, D(9,8) are used to address which register to set. The rest of the eight bits are used as control data bits. There are two control registers, CR0 and CR1, that are user configurable. All of the register bits are written to the control register during write cycles. A description of the control registers is shown in Figure 2.

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TLV1571, TLV1578 2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C ±MARCH 1999 ± REVISED FEBRUARY 2000

detailed description (continued)

control registers

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

Control Register Zero (CR0)

D7

D6

D5

D4

D3

D2

D1

D0

A(1:0)=00

STARTSEL

PROGEOC

CLKSEL

SWPWDN

MODESEL

CHSEL(2±0)²

0:

0:

0:

0:

0:

D(2± 0)

Single

Channels Swept

HARDWARE

INT

Internal

NORMAL

Single

Input

START

Clock

Channel

0h

0

0,1

(CSTART)

1:

1:

1:

EOC

Powerdown

Sweep

1:

1:

1h

1

0,1,2,3

Mode

SOFTWARE

External

2h

2

0,1,2,3,4,5,

START

Clock

3h

3

0,1,2,3,4,5,6,7

4h

4

N/A

5h

5

N/A

6h

6

N/A

7h

7

N/A

Control Register One (CR1)

D7³

D6

D5³

D4³

D3

D2

D1

D0

A(1:0)=01

RESERVED

OSCSPD

0 Reserved

0 Reserved

OUTCODE

READREG

STEST1

STEST0

0:

0:

0:

0:

0:

0:

CR1.(1±0)

IF READREG = 0

Reserved

INT. OSC.

Reserved

Reserved

Binary

Enable Self

ACTION

Bit

SLOW

Bit

Bit,

Test

0h

Output =

Always

1:

Always

Always

1:

1:

CONVERSION result

Write 0

INT. OSC.

Write 0

Write 0

Enable

1h

Output =

FAST

2s

Register

SELF TEST 1 result

Complement

Read back

2h

Output =

SELF TEST 2 result

3h

Output =

SELF TEST 3 result

IF READREG = 1

0h

Output Contents of

CR0

1h

Output Contents of

CR1

2h

RESERVED

3h

RESERVED

² Don't care for TLV1571

³ When in read back mode, the values read from the control register reserved bits are don't care.

Figure 2. Input Data Format

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TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C ±MARCH 1999 ± REVISED FEBRUARY 2000

detailed description (continued)

hardware configuration option

The TLV1571/TLV1578 can configure itself. This option is enabled when the WR pin is tied to ground and a dummy RD signal is applied. The ADC is now fully configured. Zeros or default values are applied to both control registers. The ADC is configured ideally for 3-V operation, which means the internal OSC is set at 10 MHz, single channel input mode, and hardware start of conversion using CSTART.

ADC conversion modes

The TLV1571/TLV1578 provides two conversion modes and two start of conversion modes. In single channel input mode, a single channel is continuously sampled and converted. In sweep mode (only available for the TLV1578), a predetermined set of channels is continuously sampled and converted. Table 1 explains these modes in more detail.

		Table 1. Conversion Modes
	START OF					COMMENT±SET BITS
MODES	CONVER-	OPERATION
						CR0.D(2±0) FOR INPUT
	SION
Single	Hardware	• Repeated conversions from a selected channel					rising edge must
						CSTART
Channel	Start	• CSTART falling edge to start sampling			be applied a minimum of
Input²	(CSTART)	• CSTART rising edge to start conversion			5 ns before or after CLK
CR0.D3 = 0	CR0.D7 = 0	• If in INT mode, one INT pulse generated after each conversion			rising edge.
CR1.D7 = 0		• If in EOC mode, EOC will go high to low at start of conversion, and return high
		at end of conversion.
	Software	• Repeated conversions from a selected channel			With external clock,
								WR
	Start	• WR rising edge to start sampling initially. Thereafter, sampling occurs at the rising			and RD rising edge must be
	CR0.D7 = 1	edge of RD.			a minimum 5 ns before or
		• Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INT			after CLK rising edge.
		mode, one INT pulse is generated after each conversion
		• If in EOC mode, EOC will go high to low at start of conversion and return high at
		end of conversion.
Channel	Hardware	• One conversion per channel from a predetermined sequence of channels					rising edge must
						CSTART
Sweep	Start	• CSTART falling edge to start sampling			be applied a minimum of
CR0.D3 = 1	(CSTART)	• CSTART rising edge to start conversion			5 ns before or after CLK
CR1.D7 = 0	CR0.D7 = 0	• If in INT mode, one INT pulse generated after each conversion			rising edge.
		• If in EOC mode, EOC will go high to low at start of conversion, and return high
		at end of conversion.
	Software	• One conversion per channel from a sequence of channels			With external clock,
								WR
	Start	• WR rising edge to start sampling			and RD rising edge must be
	CR0.D7 = 1	• ADC proceeds to sample next channel at rising edge of	RD.	Conversion begins	a minimum 5 ns before or
		after 6 clocks and lasts 10 clocks			after CLK rising edge.
		• If in INT mode, one INT pulse generated after each conversion
		• If in EOC mode, EOC will go high to low at start of conversion and return high at
		end of conversion.

² Single channel input mode repeatedly samples and converts from the channel until WR is applied.

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TLV1571, TLV1578 2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C ±MARCH 1999 ± REVISED FEBRUARY 2000

detailed description (continued)

configure the device

The device can be configured by writing to control registers CR0 and CR1.

Table 2. TLV1571/TLV1578 Programming Examples

REGISTER		INDEX		D7	D6	D5	D4	D3	D2	D1	D0	COMMENT
	D9		D8
EXAMPLE1
CR0	0		0	0	0	0	0	0	0	0	0	Single channel
CR1	0		1	0	0	0	0	0	1	0	0	Single Input
EXAMPLE2
CR0	0		0	0	1	1	0	1	0	1	1	Sweep mode
CR1	0		1	0	0	0	0	1	1	0	0	2's complement output

register read back

Control data written to the TLV1571/78 can be read back from the control registers CR0 and CR1. See Figure 2.

NOTE:

Data read out of CR1 reserved bits is don't care.

power down

The TLV1571/TLV1578 offers two power-down modes, auto power down and software power down. This device will automatically proceed to auto power-down mode if RD is not present one clock after conversion. Software power down is controlled directly by the userby pulling CS to DVDD.

Table 3. Power Down Modes

	PARAMETERS/MODES	AUTO POWER DOWN	SOFTWARE POWER DOWN
			(CS = DVDD)
	Maximum power down dissipation current	1 mA	10 A
	Comparator	Power down	Power down
	Clock buffer	Power down	Power down
	Reference	Active	Power down
	Control registers	Saved	Saved
	Minimum power down time	1 CLK	2 CLK
	Minimum resume time	1 CLK	2 CLK

self-test modes

The TLV1571/TLV1578 provides three self test modes. These modes can be used to check whether the ADC itself is working properly without having to supply an external signal. There are three tests that are controlled by writing to CR1(D1,D0) (see Table 4).

Table 4. Self Tests

	CR1(D1,D0)	SELF TEST VOLTAGE APPLIED	DIGITAL OUTPUT
	0h	Normal, no self test applied	N/A
	1h	VREFM applied to ADC input internally	000h
	2h	(VREFP±VREFM)/2 applied to ADC input internally	200h
	3h	VIN = VREFP applied to ADC input internally	3FFh

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TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C ±MARCH 1999 ± REVISED FEBRUARY 2000

detailed description (continued)

reference voltage input

The TLV1571/TLV1578 has two reference input pins: REFP and REFM. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. The values of REFP, REFM, and the analog input should not exceed the positive supply or be less than GND consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher than REFP and is at zero when the input signal is equal to or lower than REFM.

sampling/conversion

All sampling, conversion, and data output in the device are started by a trigger. This could be the RD, WR, or CSTART signal depending on the mode of conversion and configuration. The rising edge of RD, WR, and CSTART signal are extremely important, since they are used to start the conversion. These edges need to stay close to the rising edge of the external clock (if they are used as CLK). The minimum setup and hold time with respect to the rising edge of the external clock should be 5 ns minimum. When the internal clock is used, this is not an issue since these two edges will start the internal clock automatically. Therefore, the setup time is always met. Software controlled sampling lasts 6 clock cycles. This is done via the CLK input or the internal oscillator if enabled. The input clock frequency can be 1 MHz to 20 MHz, translating into a sampling time from 0.6 s to 0.3 s. The internal oscillator frequency is 9 MHz minimum (oscillator frequency is between 9 MHz to 22 MHz), translating into a sampling time from 0.6 s to 0.3 s. Conversion begins immediately after sampling and lasts 10 clock cycles. This is again done using the external clock input (1 MHz±20 MHz) or the internal oscillator (9 MHz minimum) if enabled. Hardware controlled sampling, via CSTART, begins on falling CSTART lasts the length of the active CSTART signal. This allows more control over the sampling time, which is useful when sampling sources with large output impedances. On rising CSTART, conversion begins. Conversion in hardware controlled mode also lasts 10 clock cycles. This is done using the external clock input (1 MHz±20 MHz) or the internal oscillator (9 MHz minimum) as is the case in software controlled mode.

ExtClk

WR

RD

	th(WRL_EXTCLKH) ≥ 5 ns
	tsu(WRH_EXTCLKH) ≥ 5 ns
OR	th(RDL_EXTCLKH) ≥ 5 ns
	tsu(RDH_EXTCLKH) ≥ 5 ns
OR
	th(CSTARTL_EXTCLKH) ≥ 5 ns
td(EXTCLK_CSTARTL) ≥ 5 ns	tsu(CSTARTH_EXTCLKH)
	≥ 5 ns

CSTART

NOTE: tsu = setup time, th = hold time

Figure 3. Trigger Timing ± Software Start Mode Using External Clock

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TLV1571, TLV1578 2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C ±MARCH 1999 ± REVISED FEBRUARY 2000

start of conversion mechanism

There are two ways to convert data: hardware and software. In the hardware conversion mode the ADC begins sampling at the falling edge of CSTART and begins conversion at the rising edge of CSTART. Software start mode ADC samples for 6 clocks, then conversion occurs for ten clocks. The total sampling and conversion process lasts only 16 clocks in this case. If RD is not detected during the next clock cycle, the ADC automatically proceeds to a power down state. Data is valid on the rising edge of INT in both conversion modes.

hardware CSTART conversion

external clock

With CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART and conversion begins at the rising edge of CSTART. At the end of conversion, EOC goes from low to high, telling the host that conversion is ready to be read out. The external clock is active and is used as the reference at all times. With this mode, it is required that CSTART is not applied at the rising edge of the clock (see Figure 4).

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