Texas Instruments TLV5604IDR, TLV5604ID, TLV5604CPWR, TLV5604CDR, TLV5604CPW Datasheet

TLV5604 2.7-V TO 5.5-V 10-BIT 3-μS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176A ± DECEMBER 1997 ± REVISED SEPTEMBER 1998

DFour 10-Bit D/A Converters

DProgrammable Settling Time of 3 ms or 9 ms Typ

DTMS320, (Q)SPI, and Microwire Compatible Serial Interface

DInternal Power-On Reset

DLow Power Consumption:

5.5 mW, Slow Mode ± 5-V Supply

3.3 mW, Slow Mode ± 3-V Supply

DReference Input Buffers

DVoltage Output Range . . . 2 × the Reference

Input Voltage

DMonotonic Over Temperature

DDual 2.7-V to 5.5-V Supply (Separate Digital and Analog Supplies)

description

The TLV5604 is a quadruple 10-bit voltage output digital-to-analog converter (DAC) with a flexible 4-wire serial interface. The 4-wire serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5604 is programmed with a 16-bit serial word comprised of a DAC address, individual DAC control bits, and a 10-bit DAC value.

DHardware Power Down (10 nA)

DSoftware Power Down (10 nA)

DSimultaneous Update

applications

DBattery Powered Test Instruments

DDigital Offset and Gain Adjustment

DIndustrial Process Controls

DMachine and Motion Control Devices

DCommunications

DArbitrary Waveform Generation

D OR PW PACKAGE

					(TOP VIEW)
DVDD								AVDD
					1	16
		PD			2	15		REFINAB
	LDAC				3	14		OUTA
	DIN				4	13		OUTB
	SCLK				5	12		OUTC
		CS			6	11		OUTD
		FS			7	10		REFINCD
DGND					8	9		AGND

The device has provision for two supplies: one digital supply for the serial interface (via pins DVDD and DGND), and one for the DACs, reference buffers and output buffers (via pins AVDD and AGND). Each supply is independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC will be controlled via a microprocessor operating on a 3-V supply (also used on pins DVDD and DGND), with the DACs operating on a 5-V supply. Of course, the digital and analog supplies can be tied together.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow DACs A and B to have a different reference voltage then DACs C and D.

The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The TLV5604C is characterized for operation from 0°C to 70°C. The TLV5604I is characterized for operation from ±40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1998, Texas Instruments Incorporated

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1

TLV5604

2.7-V TO 5.5-V 10-BIT 3-μS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176A ± DECEMBER 1997 ± REVISED SEPTEMBER 1998

AVAILABLE OPTIONS

		PACKAGE
TA
	SOIC		TSSOP
	(D)		(PW)
0°C to 70°C	TLV5604CD		TLV5604CPW
± 40°C to 85°C	TLV5604ID		TLV5604IPW

functional block diagram
						AVDD	DVDD
15						16	1
REFINAB
				DAC A
						+
		Power-On				_	x2		14
		Reset							OUTA
					10	10-Bit	10
						DAC
		Serial	14	14-Bit		Latch
	4
DIN		Input		Data
		Register		and
		2		Control	2	2-Bit
				Register		Control	2
						Data	Power Down/
	7					Latch
FS		DAC					Speed Control
	5
SCLK		Select/
		Control
	6
CS		Logic
						DAC B		13	OUTB
						DAC C		12	OUTC
REFINCD
						DAC D		11	OUTD
						3	2
		9	8
		AGND	DGND			LDAC	PD

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLV5604 2.7-V TO 5.5-V 10-BIT 3-μS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

								SLAS176A ± DECEMBER 1997 ± REVISED SEPTEMBER 1998
							Terminal Functions
		TERMINAL			I/O			DESCRIPTION
		NAME		NO.
	AGND			9		Analog ground
	AVDD			16		Analog supply
				6	I	Chip select. This terminal is active low.
	CS
	DGND			8		Digital ground
	DIN			4	I	Serial data input
	DVDD			1		Digital supply
	FS			7	I	Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out
						to the TLV5604.
				2	I	Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages.
	PD
						This terminal is active low.
				3	I	Load DAC. When the		signal is high, no DAC output updates occur when the input digital data is read into
	LDAC						LDAC
						the serial interface. The DAC outputs are only updated when LDAC is low.
	REFINAB			15	I	Voltage reference input for DACs A and B.
	REFINCD			10	I	Voltage reference input for DACs C and D.
	SCLK			5	I	Serial Clock input
	OUTA			14	O	DAC A output
	OUTB			13	O	DAC B output
	OUTC			12	O	DAC C output
	OUTD			11	O	DAC D output

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage, (DVDD, AVDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . 7	V
Supply voltage difference, (AVDD to DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±2.8 V to 2.8	V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.3 V to DVDD + 0.3	V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.3 V to AVDD + 0.3	V
Operating free-air temperature range, TA: TLV5604C . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . 0°C to 70°C
TLV5604I . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . 260°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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3

TLV5604

2.7-V TO 5.5-V 10-BIT 3-μS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176A ± DECEMBER 1997 ± REVISED SEPTEMBER 1998

recommended operating conditions

			MIN	NOM	MAX	UNIT
	Supply voltage, AVDD, DVDD	5-V supply	4.5	5	5.5	V
		3-V supply	2.7	3	3.3
	High-level digital input, VIH	DVDD = 2.7 V to 5.5 V	2			V
	Low-level digital input, VIL	DVDD = 2.7 V to 5.5 V			0.8	V
	Reference voltage, Vref to REFINAB, REFINCD terminal	5-V supply (see Note 1)	0	2.048	AVDD±1.5	V
		3-V supply (see Note 1)	0	1.024	AVDD±1.5
	Load resistance, RL		2	10		kW
	Load capacitance, CL				100	pF
	Serial clock rate, SCLK				20	MHz
	Operating free-air temperature	TLV5604C	0		70	°C
		TLV5604I	±40		85

NOTE 1: Voltages greater than AVDD/2 will cause output saturation for large DAC codes.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

static DAC specifications

	PARAMETER		TEST CONDITIONS	MIN TYP	MAX	UNIT
	Resolution			10		bits
	Integral nonlinearity (INL), end point adjusted		See Note 2		±1	LSB
	Differential nonlinearity (DNL)		See Note 3	±0.1	±1	LSB
EZS	Zero scale error (offset error at zero scale)		See Note 4		±12	mV
	Zero scale error temperature coefficient		See Note 5	10		ppm/°C
EG	Gain error		See Note 6		±0.6	%of FS
						voltage
	Gain error temperature coefficient		See Note 7	10		ppm/°C
PSRR	Power supply rejection ratio	Zero scale gain	See Notes 8 and 9	± 80		dB
		Gain		± 80

NOTES: 2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.

3.The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal

1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

4.Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

5.Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) ± EZS (Tmin)]/Vref × 106/(Tmax ± Tmin).

6.Gain error is the deviation from the ideal output (2Vref ± 1 LSB) with an output load of 10 kW excluding the effects of the zero-error.

7.Gain temperature coefficient is given by: EG TC = [EG(Tmax) ± EG (Tmin)]/Vref × 106/(Tmax ± Tmin).

8.Zero-scale-error rejection ratio (EZS±RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.5 V dc, and measuring the proportion of this signal imposed on the zero-code output voltage.

9.Gain-error rejection ratio (EG-RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.5 V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero scale change.

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLV5604 2.7-V TO 5.5-V 10-BIT 3-μS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176A ± DECEMBER 1997 ± REVISED SEPTEMBER 1998

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)

individual DAC output specifications

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
VO	Voltage output	RL = 10 kΩ	0		AVDD±0.1	V
	Output load regulation accuracy	RL = 2 kΩ vs 10 kΩ		0.1	0.25	% of FS
						voltage

reference input (REFINAB, REFINCD)

	PARAMETER	TEST CONDITIONS		MIN TYP	MAX	UNIT
VI	Input voltage range	See Note 10		0	AVDD±1.5	V
RI	Input resistance			10		MΩ
CI	Input capacitance			5		pF
	Reference feed through	REFIN = 1 Vpp at 1 kHz + 1.024 V dc		±75		dB
		(see Note 11)
	Reference input bandwidth	REFIN = 0.2 Vpp + 1.024 V dc	Slow	0.5		MHz
			Fast	1

NOTES: 10. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.

11.Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref(REFINAB or REFINCD) input = 1.024 Vdc + 1 Vpp at 1 kHz.

digital inputs (D0±D11, CS, WEB, LDAC, PD)

	PARAMETER	TEST CONDITIONS	MIN TYP	MAX	UNIT
IIH	High-level digital input current	VI = DVDD		±1	μA
IIL	Low-level digital input current	VI = 0 V		±1	μA
CI	Input capacitance		3		pF

power supply

		PARAMETER		TEST CONDITIONS		MIN TYP	MAX	UNIT
			5-V supply,	No load, Clock running	Slow	1.4	2.2	mA
	IDD	Power supply current			Fast	3.5	5.5
			3-V supply,	No load, Clock running	Slow	1	1.5	mA
					Fast	3	4.5
		Power down supply current,				10		nA
		See Figure 12

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5

TLV5604

2.7-V TO 5.5-V 10-BIT 3-μS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176A ± DECEMBER 1997 ± REVISED SEPTEMBER 1998

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)

analog output dynamic performance

		PARAMETER		TEST CONDITIONS		MIN TYP	MAX	UNIT
	SR	Output slew rate	CL = 100 pF,	RL = 10 kΩ,	Fast	5		V/μs
			VO = 10% to 90%,
					Slow	1		V/μs
			Vref = 2.048 V, 1024 V
	ts	Output settling time	To ± 0.5 LSB,	CL = 100 pF,	Fast	2.5	4	μs
			RL = 10 kΩ,	See Notes 12 and 14	Slow	8.5	18
	ts(c)	Output settling time, code to code	To ± 0.5 LSB,	CL = 100 pF,	Fast	1		μs
			RL = 10 kΩ,	See Note 13	Slow	2
		Glitch energy	Code transition from 7FF to 800			10		nV-sec
	SNR	Signal-to-noise ratio	Sinewave generated by DAC,			68
			Reference voltage = 1.024 at 3 V and 2.048 at 5 V,
	S/(N+D)	Signal to noise + distortion				65
			fs = 400 KSPS,
								dB
	THD	Total harmonic Distortion	fOUT = 1.1 kHz sinewave,			±68
			CL = 100 pF,	RL = 10 kΩ,
	SFDR	Spurious free dynamic range				70
			BW = 20 kHz

NOTES: 12. Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change of 020 hex to 3FF hex or 3FF hex to 020 hex.

13.Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change of one count, 1FF hex to 200 hex.

14.Limits are ensured by design and characterization, but are not production tested.

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TLV5604 2.7-V TO 5.5-V 10-BIT 3-μS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176A ± DECEMBER 1997 ± REVISED SEPTEMBER 1998

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)

digital input timing requirements

							MIN NOM MAX	UNIT
	tsu(CS±FS)	Setup time,	CS	low before FS↓			10	ns
	tsu(FS±CK)	Setup time, FS low before first negative SCLK edge					8	ns
	tsu(C16±FS)	Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising					10	ns
		edge of FS
		Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before				rising
					CS
	tsu(C16±CS)	edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup					10	ns
		time is between the FS rising edge and CS rising edge.
	twH	Pulse duration, SCLK high					25	ns
	twL	Pulse duration, SCLK low					25	ns
	tsu(D)	Setup time, data ready before SCLK falling edge					8	ns
	th(D)	Hold time, data held valid after SCLK falling edge					5	ns
	twH(FS)	Pulse duration, FS high					20	ns

PARAMETER MEASUREMENT INFORMATION

		twL		twH
SCLK	1	2	3	4	5	15	16
	tsu(D)	th(D)
DIN	D15	D14	D13	D12		D1	D0

tsu(FS-CK)

tsu(C16-CS)

tsu(CS-FS)

CS

twH(FS)		tsu(C16-FS)

FS

Figure 1. Timing Diagram

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7

TLV5604

2.7-V TO 5.5-V 10-BIT 3-μS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176A ± DECEMBER 1997 ± REVISED SEPTEMBER 1998

TYPICAL CHARACTERISTICS

LOAD REGULATION

	0.35	VDD = 5 V,
	0.30	VREF = 2 V,
		VO = Full Scale
V	0.25
±						5 V Slow Mode, Sink
Voltage
	0.20
					5 V Fast Mode, Sink
± Output
	0.15
O	0.10
V
	0.05
	0	0	0.02	0.04	0.1	0.2	0.4	1	2	4
				Load Current ± mA

Figure 2

LOAD REGULATION

	4.002
	4.00
	3.998	5 V Slow Mode, Source
± V	3.996
Voltage
	3.994	5 V Fast Mode, Source
± Output
	3.992
	3.99
O
V	3.988
		VDD = 5 V,
	3.986	VREF = 2 V,
		VO = Full Scale

3.984

0	0.02	0.04	0.1	0.2	0.4	1	2	4
		Load Current ± mA

Figure 4

LOAD REGULATION

	0.20	VDD = 3 V,
	0.18
		VREF = 1 V,
	0.16	VO = Full Scale
V	0.14
±						3 V Slow Mode, Sink
Voltage
	0.12
	0.10
± Output				3 V Fast Mode, Sink
	0.08
	0.06
O
V
	0.04
	0.02
	0	0	0.01	0.02	0.05	0.1	0.2	0.5	1	2

Load Current ± mA

Figure 3

LOAD REGULATION

	2.003
	2.002
	2.002	3 V Fast Mode, Source
± V
Voltage	2.001
	2.001	3 V Slow Mode, Source
Output
	2
±
O
V	2
		VDD = 3 V,
	1.999	VREF = 1 V,
		VO = Full Scale

1.999

0

0.01

0.02

0.05

0.1

0.2

0.5

1

2

Load Current ± mA

Figure 5

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLV5604 2.7-V TO 5.5-V 10-BIT 3-μS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176A ± DECEMBER 1997 ± REVISED SEPTEMBER 1998

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

						vs
				TEMPERATURE
	4
		VDD = 3 V,
	3.5	VREF = 1.024 V,
		VO = Full Scale
						Fast Mode
mA	3
±
Current	2.5
± Supply	2
	1.5
DD
I						Slow Mode
	1
	0.5	±55	±40	±25	0	25	40	70	85	125
				T ± Temperature ± °C

SUPPLY CURRENT

						vs
				TEMPERATURE
	4
	3.5					Fast Mode
mA	3
±
Current	2.5
± Supply	2
	1.5				Slow Mode
DD
I
	1	VDD = 5 V,
		VREF = 1.024 V,
		VO = Full Scale
	0.5	±55	±40	±25	0	25	40	70	85	125
				T ± Temperature ± °C

Figure 6

Figure 7

TOTAL HARMONIC DISTORTION

TOTAL HARMONIC DISTORTION

vs

vs

FREQUENCY

FREQUENCY

0

0

±10

Vref = 1 V dc + 1 V p/p Sinewave,

Vref = 1 V dc + 1 V p/p Sinewave,

HarmonicTotal±THD Distortion ± dB

Output Full Scale

HarmonicTotal±THD Distortion ± dB

±10

Output Full Scale

±70

±20

±20

±30

±30

±±40

±±40

±50

±50

±60

Fast Mode

±60

Slow Mode

±70

±80

±80

0

5

10

20

30

50

100

0

5

10

20

30

50

100

f ± Frequency ± kHz

f ± Frequency ± kHz

Figure 8

Figure 9

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9