Texas Instruments SN74ABT843DBLE, SN74ABT843DBR, SN74ABT843DW, SN74ABT843DWR, SN74ABT843NT Datasheet

SN54ABT843, SN74ABT843 9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

	SCBS197D ± FEBRUARY 1991 ± REVISED MAY 1997
D State-of-the-Art EPIC-ΙΙB BiCMOS Design	SN54ABT843 . . . JT OR W PACKAGE
Significantly Reduces Power Dissipation	SN74ABT843 . . . DB, DW, OR NT PACKAGE
	(TOP VIEW)

DLatch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17				1	24
		OE					VCC
D Typical VOLP (Output Ground Bounce) < 1 V		1D		2	23		1Q
at VCC = 5 V, TA = 25°C		2D		3	22		2Q
D High-Drive Outputs (±32-mA IOH, 64-mA IOL)		3D		4	21		3Q
D Package Options Include Plastic		4D		5	20		4Q
Small-Outline (DW) and Shrink		5D		6	19		5Q
				7	18
Small-Outline (DB) Packages, Ceramic Chip		6D					6Q
Carriers (FK), Ceramic Flat (W) Package,		7D		8	17		7Q
and Plastic (NT) and Ceramic (JT) DIPs		8D		9	16		8Q
		9D		10	15		9Q

description	CLR			11	14			PRE
	GND			12	13			LE

The 'ABT843 9-bit latches are designed

specifically for driving highly capacitive or

SN54ABT843 . . . FK PACKAGE

relatively

low-impedance

loads.

They

are

particularly suitable for implementing buffer

(TOP VIEW)

CC

registers, I/O ports, bidirectional bus drivers, and

2D

1D

OE

NC

2Q

working registers.

V 1Q

The nine transparent D-type latches provide true

3D

4

3

2

1

28 27 26

3Q

data at the outputs.

5

25

4D

6

24

4Q

A buffered output-enable (OE) input can be used

5D

7

23

5Q

to place the nine outputs in either a normal logic

NC

8

22

NC

state

(high

or

low

logic

levels)

or

a

6D

9

21

6Q

high-impedance state. The outputs are also in the

7D

10

20

7Q

high-impedance state during power-up and

8D

11

19

8Q

power-down conditions. The outputs remain in the

12 13 14 15 16 17 18

high-impedance state while the device is powered

9D

CLR

GND

NC

LE PRE

9Q

down. In the high-impedance state, the outputs

neither load nor drive the bus lines significantly.

NC ± No internal connection

The high-impedance state and increased drive

provide the capability to drive bus lines without

need for interface or pullup components.

OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT843 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT843 is characterized for operation from ±40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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SN54ABT843, SN74ABT843

9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

SCBS197D ± FEBRUARY 1991 ± REVISED MAY 1997

FUNCTION TABLE

				INPUTS					OUTPUT
							LE	D	Q
	PRE		CLR		OE
	L		X		L		X	X	H
	H		L		L		X	X	L
	H		H		L		H	L	L
	H		H		L		H	H	H
	H		H		L		L	X	Q0
	X		X		H		X	X	Z

logic symbol²

			1			EN
		OE
14						S2
	PRE
11						R
	CLR
13						C1
		LE
2										23
		1D				1D		2			1Q
3										22
		2D									2Q
4										21
		3D									3Q
5										20
		4D									4Q
6										19
		5D									5Q
7										18
		6D									6Q
8										17
		7D									7Q
9										16
		8D									8Q
10										15
		9D									9Q

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, and W packages.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABT843, SN74ABT843 9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

SCBS197D ± FEBRUARY 1991 ± REVISED MAY 1997

logic diagram (positive logic)

OE	1
PRE	14
CLR	11
LE	13
		S2
		C1	23
1D	2	1D	1Q
		R

To Eight Other Channels

Pin numbers shown are for the DB, DW, JT, NT, and W packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range , VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . .	±0.5 V to 5.5	V
Current into any output in the low state, IO: SN54ABT843 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 96 mA
SN74ABT843 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 104°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 81°C/W
NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±65°C to 150°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. This is a stress ratingonly, and functional operation of the device at these or any other conditions beyond those indicated in the ªrecommended operating conditionsº section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2.The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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