Texas Instruments SN74ABT7820-15PH, SN74ABT7820-15PN, SN74ABT7820-20PH, SN74ABT7820-20PN, SN74ABT7820-25PH Datasheet

SN74ABT7820 512 ×18 ×2

STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS206D ± AUGUST 1991 ± REVISED APRIL 1998

D Member of the Texas Instruments	D
Widebus Family	D

DAdvanced BiCMOS Technology

DIndependent Asynchronous Inputs and

Outputs	D
D Two Separate 512 × 18 FIFOs Buffering	D
Data in Opposite Directions

DProgrammable Almost-Full/Almost-Empty Flags

Empty, Full, and Half-Full Flags

Fast Access Times of 12 ns With a 50-pF Load and Simultaneous Switching Data Outputs

Supports Clock Rates up to 67 MHz

Package Options Include 80-Pin Quad Flat

(PH) and 80-Pin Thin Quad Flat (PN)

Packages

PH PACKAGE (TOP VIEW)

GBA

SBA

GND

LDCKA

UNCKB

EMPTYB

V

V

V

V

EMPTYA UNCKA

LDCKB

GND

SAB

GAB

CC

CC

CC

CC

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

1

64

RSTA

RSTB

PENA

2

63

PENB

AF/AEA

3

62

AF/AEB

4

HFA

61

HFB

5

FULLA

60

FULLB

6

GND

59

GND

7

A0

58

B0

8

A1

57

B1

9

VCC

56

VCC

10

A2

55

B2

A3

11

54

B3

GND

12

53

GND

A4

13

52

B4

A5

14

51

B5

15

GND

50

GND

16

A6

49

B6

17

A7

48

B7

18

GND

47

GND

19

46

A8

B8

20

A9

45

B9

21

VCC

44

VCC

22

A10

43

B10

A11

23

42

B11

GND

24

41

GND

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

A13

V

A14

A15

GND

A16

A17

B17

B16

GND B15

B14

V

B13

B12

A12

CC

CC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1998, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN74ABT7820 512 ×18 ×2

STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS206D ± AUGUST 1991 ± REVISED APRIL 1998

PN PACKAGE (TOP VIEW)

PENA

RSTA

GBA SBA

GND

LDCKA

UNCKB

EMPTYB

V

V

V

V

EMPTYA

UNCKA

LDCKB

GND

SAB GAB

RSTB

PENB

CC

CC

CC

CC

AF/AEA

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

AF/AEB

1

60

HFA

2

59

HFB

FULLA

3

58

FULLB

GND

4

57

GND

A0

5

56

B0

A1

6

55

B1

VCC

7

54

VCC

A2

8

53

B2

A3

9

52

B3

GND

10

51

GND

A4

11

50

B4

A5

12

49

B5

GND

13

48

GND

A6

14

47

B6

A7

15

46

B7

GND

16

45

GND

A8

17

44

B8

A9

18

43

B9

VCC

19

42

VCC

A10

20

41

B10

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

A11

GND

A12 A13

V

A14

A15

GND

A16

A17

B17

B16

GND

B15

B14

V

B13 B12

GND

B11

CC

CC

description

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ABT7820 is arranged as two 512 ×18-bit FIFOs for high speed and fast access times. It processes data at rates up to 67 MHz with access times of 12 ns in a bit-parallel format.

The SN74ABT7820 consists of bus-transceiver circuits, two 512 ×18 FIFOs, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable inputs (GAB and GBA) control the transceiver functions. The SAB and SBA control inputs select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the eight fundamental bus-management functions that can be performed with the SN74ABT7820.

The SN74ABT7820 is characterized for operation from 0°C to 70°C.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

								SN74ABT7820
								512 ×18	×2
			STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
					SCAS206D ± AUGUST 1991 ± REVISED APRIL 1998
	FIFO A					FIFO A
In		Out			In		Out
Bus A			Bus B	Bus A				Bus B
	FIFO B					FIFO B
Out		In			Out		In
SAB	SBA	GAB GBA			SAB	SBA	GAB GBA
L	X	H	L		X	X	L	L
	FIFO A					FIFO A
	In	Out			In		Out
Bus A			Bus B	Bus A				Bus B
	FIFO B					FIFO B
	Out	In			Out		In
SAB	SBA	GAB GBA			SAB	SBA	GAB GBA
X	L	L	H		H	L	H	H
	FIFO A					FIFO A
In		Out			In		Out
Bus A			Bus B	Bus A				Bus B
	FIFO B					FIFO B
Out		In			Out		In
SAB	SBA	GAB GBA			SAB	SBA	GAB GBA
H	X	H	L		L	H	H	H
	FIFO A					FIFO A
	In	Out				In	Out
Bus A			Bus B	Bus A				Bus B
	FIFO B					FIFO B
	Out	In				Out	In

SAB	SBA	GAB GBA		SAB	SBA	GAB GBA
X	H	L	H	H	H	H	H

Figure 1. Bus-Management Functions

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

SN74ABT7820 512 ×18 ×2

STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS206D ± AUGUST 1991 ± REVISED APRIL 1998

SELECT-MODE CONTROL TABLE

CONTROL		OPERATION
SBA	SAB	A BUS	B BUS
L	L	Real-time B-to-A bus	Real-time A-to-B bus
H	L	FIFO B-to-A bus	Real-time A-to-B bus
L	H	Real-time B-to-A bus	FIFO A-to-B bus
H	H	FIFO B-to-A bus	FIFO A-to-B bus

OUTPUT-ENABLE CONTROL TABLE

CONTROL		OPERATION
GBA	GAB	A BUS	B BUS
L	L	Isolation/input to A bus	Isolation/input to B bus
H	L	A bus enabled	Isolation/input to B bus
L	H	Isolation/input to A bus	B bus enabled
H	H	A bus enabled	B bus enabled

Figure 1. Bus-Management Functions (Continued)

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

				SN74ABT7820
				512	×18	×2
	STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
				SCAS206D ± AUGUST 1991 ± REVISED APRIL 1998
logic symbol²
			F
66			FIFO
	1	512 × 18 × 2
SAB		SN74ABT7820
79	MODE
SBA	0
65	EN1
GAB
80	EN2
GBA
1				64
RSTA	RESET A		RESET B	RSTB
2				63
PENA	PROG ENA		PROG ENB	PENB
77			LDCKB	68
LDCKA	LDCKA			LDCKB
69				76
UNCKA	UNCKA		UNCKB	UNCKB
5	FULLA		FULLB	60
FULLA				FULLB
70	EMPTYA		EMPTYB	75
EMPTYA				EMPTYB
3	ALMOST FULL/		ALMOST FULL/	62
AF/AEA				AF/AEB
	ALMOST EMPTY A		ALMOST EMPTY B
4				61
	HALF-FULL A		HALF-FULL B
HFA				HFB
7	0		0	58
A0				B0
8				57
A1				B1
10				55
A2				B2
11				54
A3				B3
13				52
A4				B4
14				51
A5				B5
16				49
A6				B6
17				48
A7				B7
19				46
A8				B8
20	A Data		B Data	45
A9				B9
22				43
A10				B10
23				42
A11				B11
25				40
A12				B12
26				39
A13				B13
28				37
A14				B14
29				36
A15				B15
31				34
A16				B16
32	17		17	33
A17				B17

²This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the PH package.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5