Texas Instruments SN74ACT32D, SN74ACT32DBLE, SN74ACT32DBR, SN74ACT32DR, SN74ACT32N Datasheet

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Texas Instruments SN74ACT32D, SN74ACT32DBLE, SN74ACT32DBR, SN74ACT32DR, SN74ACT32N Datasheet

 

 

 

 

 

SN54ACT32, SN74ACT32

 

QUADRUPLE 2-INPUT POSITIVE-OR GATES

 

SCAS530A ± AUGUST 1995 ± REVISED MAY 1996

 

 

 

 

 

 

 

 

D Inputs Are TTL-Voltage Compatible

SN54ACT32 . . . J OR W PACKAGE

D EPIC (Enhanced-Performance Implanted

SN74ACT32 . . . D, DB, N, OR PW PACKAGE

 

(TOP VIEW)

 

 

 

CMOS) 1- m Process

 

 

 

 

 

 

 

 

 

 

 

 

D Package Options Include Plastic

1A

 

1

14

 

VCC

 

 

Small-Outline (D), Shrink Small-Outline

1B

 

2

13

 

4B

(DB), and Thin Shrink Small-Outline (PW)

1Y

 

3

12

 

4A

Packages, Ceramic Chip Carriers (FK) and

2A

4

11

 

4Y

Flatpacks (W), and Standard Plastic (N) and

2B

 

 

 

 

 

3B

5

10

 

Ceramic (J) DIPS

2Y

 

 

 

 

 

3A

 

6

9

 

 

GND

7

8

 

3Y

description

The 'ACT32 are quadruple 2-input positive-OR gates. The devices perform the Boolean function Y = A + B or Y = A B in positive logic.

The SN54ACT32 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ACT32 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (EACH GATE)

INPUTS

OUTPUT

A

B

Y

 

 

 

H

X

H

X

H

H

L

L

L

 

 

 

SN54ACT32 . . . FK PACKAGE

(TOP VIEW)

 

1B

1A

NC

CC

4B

 

 

V

 

1Y

3

2

1

20 19

4A

4

 

 

 

18

NC

5

 

 

 

17

NC

2A

6

 

 

 

16

4Y

NC

7

 

 

 

15

NC

2B

8

 

 

 

14

3B

 

9

10 11 12 13

 

 

2Y

GND

NC

3Y

3A

 

NC ± No internal connection

logic symbol²

 

 

 

logic diagram (positive logic)

1

 

 

 

 

 

 

 

 

1A

 

1

3

1Y

A

 

 

 

 

 

 

 

2

 

 

 

 

 

 

Y

 

 

 

 

 

 

 

 

1B

 

 

 

 

B

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2A

 

 

6

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

2Y

 

 

 

 

 

 

 

 

 

 

 

 

2B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3A

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

3Y

 

 

 

 

 

 

 

 

 

 

 

 

3B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4A

 

 

11

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

4Y

 

 

 

 

 

 

 

 

 

 

 

 

4B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

²This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, J, N, PW, and W packages.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1996, Texas Instruments Incorporated

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

1

SN54ACT32, SN74ACT32

QUADRUPLE 2-INPUT POSITIVE-OR GATES

SCAS530A ± AUGUST 1995 ± REVISED MAY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . ±0.5 V to 7

V

Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±0.5 V to VCC + 0.5

V

Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±0.5 V to VCC + 0.5

V

Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . ±20 mA

Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . ±20 mA

Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . ±50 mA

Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . ±200 mA

Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . .

. . . . . . . . . . . . 1.25 W

DB package . . . . . .

. . . . . . . . . . . . . 0.5 W

N package . . . . . . .

. . . . . . . . . . . . . 1.1 W

PW package . . . . . .

. . . . . . . . . . . . . 0.5 W

Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . ±65°C to 150°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2.The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.

recommended operating conditions (see Note 3)

 

 

SN54ACT32

SN74ACT32

UNIT

 

 

 

 

 

 

 

 

MIN

MAX

MIN

MAX

 

 

 

 

 

 

 

 

 

 

VCC

Supply voltage

4.5

5.5

4.5

5.5

V

VIH

High-level input voltage

2

 

2

 

V

VIL

Low-level input voltage

 

0.8

 

0.8

V

VI

Input voltage

0

VCC

0

VCC

V

VO

Output voltage

0

VCC

0

VCC

V

IOH

High-level output current

 

±24

 

±24

mA

IOL

Low-level output current

 

24

 

24

mA

t/ v

Input transition rise or fall rate

0

8

0

8

ns/V

 

 

 

 

 

 

 

TA

Operating free-air temperature

±55

125

±40

85

°C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

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POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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