Texas Instruments SN74ACT3631-15PCB, SN74ACT3631-15PQ, SN74ACT3631-20PCB, SN74ACT3631-20PQ, SN74ACT3631-30PCB Datasheet

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SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Free-Running CLKA and CLKB Can Be

Asynchronous or Coincident

Clocked FIFO Buffering Data From Port A

to Port B

Synchronous Read-Retransmit Capability

Mailbox Register in Each Direction

Programmable Almost-Full and

Almost-Empty Flags

Microprocessor Interface Control Logic

Input-Ready and Almost-Full Flags

Synchronized by CLKA

Output-Ready and Almost-Empty Flags

Synchronized by CLKB

Low-Power 0.8-µm Advanced CMOS

Technology

Supports Clock Frequencies up to 67 MHz

Fast Access Times of 11 ns

Pin-to-Pin Compatible With the

SN74ACT3641 and SN74ACT3651

Package Options Include 120-Pin Thin

Quad Flat (PCB) and 132-Pin Plastic Quad

Flat (PQ) Packages

description

The SN74ACT3631 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies

up to 67 MHz and has read access times as fast as 1 1 ns. The 512 × 36 dual-port SRAM FIFO buffers data from

port A to port B. The FIFO memory has retransmit capability , which allows previously read data to be accessed

again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and

almost empty) to indicate when a selected number of words is stored in memory . Communication between each

port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail

has been stored. Two or more devices can be used in parallel to create wider datapaths. Expansion also is

possible in word depth.

The SN74ACT3631 is a clocked FIFO, which means each port employs a synchronous interface. All data

transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable

signals. The continuous clocks for each port are independent of one another and can be asynchronous or

coincident. The enables for each port are arranged to provide a simple interface between microprocessors

and/or buses with synchronous control.

The input-ready (IR) flag and almost-full (AF

) flag of the FIFO are two-stage synchronized to CLKA. The

output-ready (OR) flag and almost-empty (AE

) flag of the FIFO are two-stage synchronized to CLKB. Offset

values for the AF and AE flags of the FIFO can be programmed from port A or through a serial input.

The SN74ACT3631 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the following application reports:

FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering

(literature number SCAA007)

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number

SCAA007)

Metastability Performance of Clocked FIFOs (literature number SCZA004).

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCB PACKAGE

(TOP VIEW)

A35

A34

A33

A32

A31

A30

GND

A29

A28

A27

A26

A25

A24

A23

GND

A22

A21

A20

A19

A18

GND

A17

A16

A15

A14

A13

A12

B35

B34

B33

B32

GND

B31

B30

B29

B28

B27

B26

B25

B24

GND

B23

B22

B21

B20

B19

B18

GND

B17

B16

B15

B14

B13

B12

GND

CLKA

ENA

GND

A1 1

A10

CSA

MBA

GND

FS0/SD

FS1/SEN

RTM

MBF1

GND

W/RA

GND

CSB

W/RB

ENB

CLKB

B10

RST

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

MBB

GND

B1 1

MBF2

RFM

NC – No internal connection

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

5251 83828180797877767574737271706968676665646362616059585756555453

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

B35

B34

B33

B32

GND

B31

B30

B29

B28

B27

B26

B25

B24

GND

B23

B22

B21

B20

B19

B18

GND

B17

B16

B15

B14

B13

B12

GND

A35

A34

A33

A32

A31

A30

GND

A29

A28

A27

A26

A25

A24

A23

GND

A22

A21

A20

A19

A18

GND

A17

A16

A15

A14

A13

A12

PQ PACKAGE

†

(TOP VIEW)

CLKB

ENB

W/RB

GND

MBF1

GND

MBB

RTM

FS1/SEN

FS0/SD

GND

RST

MBA

MBF2

CSA

W/RA

ENA

CLKA

GND

B1 1

B10

GND

A10

A1 1

GND

RFM

CSB

NC – No internal connection

†

Uses Yamaichi socket IC51-1324-828

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Port-A

Control

Logic

CLKA

CSA

W/RA

ENA

MBA

Reset

Logic

RST

512 × 36

SRAM

Input Register

Output Register

Mail1

Write

Pointer

Read

Pointer

Status-Flag

Logic

Flag-Offset

Mail2

Port-B

Control

Logic

FS0/SD

FS1/SEN

A0–A35

MBF2

MBF1

B0–B35

CLKB

CSB

W/RB

ENB

MBB

Synch

Retransmit

Logic

RTM

RFM

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

I/O DESCRIPTION

A0–A35 I/O Port-A data. The 36-bit bidirectional data port for side A.

AE O

Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less

than or equal to the value in the almost-empty offset register (X).

AF O

Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO

is less than or equal to the value in the almost-full offset register (Y).

B0–B35 I/O Port-B data. The 36-bit bidirectional data port for side B.

CLKA I

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous

or coincident to CLKB. IR and AF

are synchronous to the low-to-high transition of CLKA.

CLKB I

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous

or coincident to CLKA. OR and AE

are synchronous to the low-to-high transition of CLKB.

CSA I

Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The

A0–A35 outputs are in the high-impedance state when CSA

is high.

CSB I

Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The

B0–B35 outputs are in the high-impedance state when CSB

is high.

ENA I Port-A master enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.

ENB I Port-B master enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.

FS1/SEN,

FS0/SD

Flag offset select 1/serial enable, flag offset select 0/serial data. FS1/SEN and FS0/SD are dual-purpose inputs used

for flag offset register programming. During a device reset, FS1/SEN

and FS0/SD select the flag offset programming

method. Three offset register programming methods are available: automatically load one of two preset values, parallel

load from port A, and serial load.

When serial load is selected for flag offset register programming, FS1/SEN

is used as an enable synchronous to the

low-to-high transition of CLKA. When FS1/SEN

is low, a rising edge on CLKA loads the bit present on FS0/SD into the

X- and Y -offset registers. The number of bit writes required to program the offset register is 18. The first bit write stores

the Y-register MSB and the last bit write stores the X-register LSB.

IR O

Input-ready flag. IR is synchronized to the low-to-high transition of CLKA. When IR is low, the FIFO is full and writes

to its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the

point of the retransmit data and prevents further writes. IR is set low during reset and is set high after reset.

MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.

MBB I

Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the

B0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects

FIFO data for output.

MBF1 O

Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register . MBF1

is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high by

a reset.

MBF2 O

Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register . MBF2

is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high by

a reset.

OR O

Output-ready flag. OR is synchronized to the low-to-high transition of CLKB. When OR is low, the FIFO is empty and

reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during

the reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory.

RFM I

Read from mark. When the FIFO is in retransmit mode, a high on RFM enables a low-to-high transition of CLKB to reset

the read pointer to the beginning retransmit location and output the first selected retransmit data.

RST I

Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur

while RST

is low. The low-to-high transition of RST latches the status of FS0 and FS1 for AF and AE offset selection.

RTM I

Retransmit mode. When RTM is high and valid data is present in the FIFO output register (OR is high), a low-to-high

transition of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected

word remains the initial retransmit point until a low-to-high transition of CLKB occurs while RTM is low , taking the FIFO

out of retransmit mode.

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME

I/O DESCRIPTION

W/RA I

Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a

low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/R

A is high.

W/RB I

Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a

low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W

/RB is low.

detailed description

reset

The SN74ACT3631 is reset by taking the reset (RST

) input low for at least four port-A clock (CLKA) and four

port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A reset

initializes the memory read and write pointers and forces the input-ready (IR) flag low, the output-ready (OR)

flag high, the almost-empty (AE

) flag low, and the almost-full (AF) flag high. Resetting the device also forces

the mailbox flags (MBF1

, MBF2) high. After a FIFO is reset, its input-ready flag is set high after at least two clock

cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory.

almost-empty flag and almost-full flag offset programming

Two registers in the SN74ACT3631 are used to hold the of fset values for the almost-empty and almost-full flags.

The almost-empty (AE

) flag offset register is labeled X, and the almost-full (AF) flag of fset register is labeled Y.

The offset registers can be loaded with a value in three ways: one of two preset values is loaded into the offset

registers, parallel load from port A, or serial load. The offset register programming mode is chosen by the flag

select (FS1, FS0) inputs during a low-to-high transition on the RST

input (see Table 1).

Table 1. Flag Programming

FS1 FS0 RST

X AND Y REGISTERS

†

H H ↑ Serial load

H L ↑ 64

L H ↑ 8

L L ↑ Parallel load from port A

†

X register holds the offset for AE

; Y register holds the

offset for AF

preset values

If a preset value of 8 or 64 is chosen by FS1 and FS0 at the time of a RST low-to-high transition according to

Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is

necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on CLKA.

parallel load from port A

To program the X and Y registers from port A, the device is reset with FS0 and FS1 low during the low-to-high

transition of RST

. After this reset is complete, the IR flag is set high after two low-to-high transitions on CLKA.

The first two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X.

Each offset register of the SN74ACT3631 uses port-A inputs (A8 –A0). The highest number input is used as

the most-significant bit of the binary number in each case. Each register value can be programmed from 1 to

508. After both offset registers are programmed from port A, subsequent FIFO writes store data in the SRAM.

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

serial load

To serially program the X and Y registers, the device is reset with FS0/SD and FS1/SEN high during the

low-to-high transition of RST

. After this reset is complete, the X- and Y -register values are loaded bitwise through

FS0/SD on each low-to-high transition of CLKA that FS1/SEN

is low. W rites of 18 bits are needed to complete

the programming. The first bit write stores the most-significant bit of the Y register, and the last bit write stores

the least-significant bit of the X register. Each register value can be programmed from 1 to 508.

When the option to program the offset registers serially is chosen, the input-ready (IR) flag remains low until

all register bits are written. The IR flag is set high by the low-to-high transition of CLKA after the last bit is loaded

to allow normal FIFO operation.

FIFO write/read operation

The state of the port-A data (A0 –A35) outputs is controlled by the port-A chip select (CSA

) and the port-A

write/read select (W/R

A). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is

high. The A0–A35 outputs are active when both CSA

and W/RA are low.

Data is loaded into the FIFO from the A0–A35 inputs on a low-to-high transition of CLKA when CSA

and the

port-A mailbox select (MBA) are low, W/R

A, the port-A enable (ENA), and the input-ready (IR) flag are high

(see Table 2). Writes to the FIFO are independent of any concurrent FIFO reads.

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA CLKA

A0–A35 OUTPUTS PORT FUNCTION

H X X X X In high-impedance state None

L H L X X In high-impedance state None

L H H L ↑ In high-impedance state FIFO write

L H H H ↑ In high-impedance state Mail1 write

L L L L X Active, mail2 register None

L L H L ↑ Active, mail2 register None

L L L H X Active, mail2 register None

L L H H ↑ Active, mail2 register Mail2 read (set MBF2 high)

The port-B control signals are identical to those of port A, with the exception that the port-B write/read select

/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0–B35) outputs is

controlled by the port-B chip select (CSB

) and the port-B write/read select (W/RB). The B0–B35 outputs are

in the high-impedance state when either CSB

is high or W/RB is low. The B0–B35 outputs are active when CSB

is low and W/RB is high.

Data is read from the FIFO to its output register on a low-to-high transition of CLKB when CSB

and the port-B

mailbox select (MBB) are low, W

/RB, the port-B enable (ENB), and the output-ready (OR) flag are high

(see Table 3). Reads from the FIFO are independent of any concurrent FIFO writes.

SN74ACT3631

512 × 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FIFO write/read operation (continued)

Table 3. Port-B Enable Function Table

CSB W/RB ENB MBB CLKB

B0–B35 OUTPUTS PORT FUNCTION

H X X X X In high-impedance state None

L L L X X In high-impedance state None

L L H L ↑ In high-impedance state None

L L H H ↑ In high-impedance state Mail2 write

L H L L X Active, FIFO output register None

L H H L ↑ Active, FIFO output register FIFO read

L H L H X Active, mail1 register None

L H H H ↑ Active, mail1 register Mail1 read (set MBF1 high)

The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only

for enabling write and read operations and are not related to high-impedance control of the data outputs. If a

port enable is low during a clock cycle, the port-chip select and write/read select can change states during the

setup- and hold-time window of the cycle.

When the output-ready (OR) flag is low, the next data word is sent to the FIFO output register automatically by

the CLKB low-to-high transition that sets the output-ready flag high. When OR is high, an available data word

is clocked to the FIFO output register only when a FIFO read is selected by the port-B chip select (CSB

write/read select (W

/RB), enable (ENB), and mailbox select (MBB).

synchronized FIFO flags

Each FIFO flag is synchronized to its port clock through at least two flip-flop stages. This is done to improve the

flags’ reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate

asynchronously to one another .

OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA.

Table 4 shows the relationship of each flag to the number of words stored in memory.

Table 4. FIFO Flag Operation

NUMBER OF WORDS IN

SYNCHRONIZED

TO CLKB

SYNCHRONIZED

TO CLKA

FIFO

†‡

OR AE AF IR

0 L L H H

1 to X H LHH

(X + 1) to [512 – (Y + 1)] H HHH

(512 – Y) to 511 H HLH

512 H H L L

†

X is the almost-empty offset for AE. Y is the almost-full offset for AF.

‡

When a word is present in the FIFO output register, its previous memory

location is free.

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