Texas Instruments SN74ABT652DBLE, SN74ABT652DBR, SN74ABT652DW, SN74ABT652DWR, SN74ABT652NT Datasheet

SN54ABT652, SN74ABT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SCBS070D ± JULY 1991 ± REVISED JULY 1994

•State-of-the-Art EPIC-ΙΙB BiCMOS Design

Significantly Reduces Power Dissipation

•ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

•Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17

•Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C

•High-Drive Outputs (±32-mA IOH, 64-mA IOL )

•Package Options Include Plastic Small-Outline ((DW)) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs

SN54ABT652 . . . JT PACKAGE

SN74ABT652 . . . DB, DW, OR NT PACKAGE

		(TOP VIEW)
CLKAB						VCC
		1	24
SAB		2	23			CLKBA
OEAB		3	22			SBA
A1		4	21
						OEBA
A2		5	20			B1
A3		6	19			B2
A4		7	18			B3
A5		8	17			B4
A6		9	16			B5
A7		10	15			B6
A8		11	14			B7
GND		12	13			B8

SN54ABT652 . . . FK PACKAGE

(TOP VIEW)

description

These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers.

Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ′ABT652.

	OEAB	SAB	CLKAB	NC	CC	CLKBA	SBA
					V
	4	3	2	1	28	27 26
A1	5						25	OEBA
A2	6						24	B1
A3	7						23	B2
NC	8						22	NC
A4	9						21	B3
A5	10						20	B4
A6	11						19	B5
	12 13 14 15 16 17 18
	A7	A8	GND	NC	B8	B7	B6

NC ± No internal connection

Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the selector enable-control pins. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.

To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver (B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver (A to B).

The SN74ABT652 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1994, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

2±1

SN54ABT652, SN74ABT652

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS070D ± JULY 1991 ± REVISED JULY 1994

description (continued)

The SN54ABT652 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT652 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE

			INPUTS				DATA I/O²		OPERATION OR FUNCTION
	OEAB	OEBA	CLKAB	CLKBA	SAB	SBA	A1 THRU A8	B1 THRU B8
	L	H	H or L	H or L	X	X	Input	Input	Isolation
	L	H	↑	↑	X	X	Input	Input	Store A and B data
	X	H	↑	H or L	X	X	Input	Unspecified³	Store A, hold B
	H	H	↑	↑	X³	X	Input	Output	Store A in both registers
	L	X	H or L	↑	X	X	Unspecified³	Input	Hold A, store B
	L	L	↑	↑	X	X³	Output	Input	Store B in both registers
	L	L	X	X	X	L	Output	Input	Real-time B data to A bus
	L	L	X	H or L	X	H	Output	Input	Stored B data to A bus
	H	H	X	X	L	X	Input	Output	Real-time A data to B bus
	H	H	H or L	X	H	X	Input	Output	Stored A data to B bus
	H	L	H or L	H or L	H	H	Output	Output	Stored A data to B bus and
									stored B data to A bus

²The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs.

³Select control = L; clocks can occur simultaneously.

Select control = H; clocks must be staggered in order to load both registers.

2±2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABT652, SN74ABT652

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS070D ± JULY 1991 ± REVISED JULY 1994

BUS A

BUS B

BUS A

BUS B

3

21

1

23

2

22

3

21

1

23

2

22

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

L

L

X

X

X

L

H

H

X

X

L

X

REAL-TIME TRANSFER

REAL-TIME TRANSFER

BUS B TO BUS A

BUS A TO BUS B

BUS A

BUS B

BUS A

BUS B

3

21

1

23

2

22

3

21

1

23

2

22

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

X

H

↑

X

X

X

H

L

L

L

H

H

L

X

X

↑

X

X

L

H

↑

↑

X

X

STORAGE FROM

TRANSFER STORED DATA

A, B, OR A AND B

TO A AND/OR B

Figure 1. Bus-Management Functions

Pin numbers shown are for the DB, DW, JT, and NT packages.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

2±3

SN54ABT652, SN74ABT652

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS070D ± JULY 1991 ± REVISED JULY 1994

logic symbol²

				21
		OEBA			EN1 [BA]
			3
	OEAB				EN2 [AB]
			23
	CLKBA					C4
			22
		SBA			G5
			1
	CLKAB					C6
			2
		SAB			G7

					20
4	≥	1	5	4D	B1
A1	1		5	1
	6D		7	≥ 1
	1		7	2
5					19
A2					B2
6					18
A3					B3
7					17
A4					B4
8					16
A5					B5
9					15
A6					B6
10					14
A7					B7
11					13
A8					B8

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, and NT packages.

2±4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265