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SN54ACT374, SN74ACT374 |
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OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS |
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WITH 3-STATE OUTPUTS |
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SCAS539E ± OCTOBER 1995 ± REVISED JANUARY 2000 |
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D Inputs Are TTL-Voltage Compatible |
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SN54ACT374 . . . J OR W PACKAGE |
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D |
EPIC (Enhanced-Performance Implanted |
SN74ACT374 . . . DB, DW, N, OR PW PACKAGE |
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(TOP VIEW) |
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CMOS) 1- m Process |
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D Package Options Include Plastic |
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OE |
1 |
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20 |
VCC |
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Small-Outline (DW) Shrink Small-Outline |
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1Q |
2 |
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19 |
8Q |
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(DB), and Thin Shrink Small-Outline (PW) |
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1D |
3 |
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18 |
8D |
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Packages, Ceramic Chip Carriers (FK) and |
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2D |
4 |
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17 |
7D |
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Flatpacks (W), and Standard Plastic (N) and |
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2Q |
5 |
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16 |
7Q |
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Ceramic (J) DIPs |
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3Q |
6 |
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15 |
6Q |
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description |
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3D |
7 |
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14 |
6D |
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4D |
8 |
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13 |
5D |
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These |
8-bit |
flip-flops |
feature |
3-state |
outputs |
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4Q |
9 |
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12 |
5Q |
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GND |
10 |
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11 |
CLK |
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designed specifically for driving highly capacitive |
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or relatively low-impedance loads. The devices |
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are particularly suitable for implementing buffer |
SN54ACT374 . . . FK PACKAGE |
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registers, I/O ports, bidirectional bus drivers, and |
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(TOP VIEW) |
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working registers. |
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1D |
1Q |
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CC |
8Q |
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The eight flip-flops of the 'ACT374 devices are |
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OE V |
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D-type edge-triggered flip-flops. On the positive |
2D |
3 |
2 |
1 |
20 19 |
8D |
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transition of the clock (CLK) input, the Q outputs |
4 |
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18 |
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are set to the logic levels set up at the data (D) |
2Q |
5 |
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17 |
7D |
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inputs. |
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3Q |
6 |
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16 |
7Q |
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A buffered output-enable (OE) input can be used |
3D |
7 |
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15 |
6Q |
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4D |
8 |
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14 |
6D |
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to place the eight outputs in either a normal logic |
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9 |
10 11 12 13 |
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state |
(high |
or |
low |
logic |
levels) |
or |
the |
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4Q |
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GND |
CLK |
5Q |
5D |
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high-impedance state. In the high-impedance |
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state, the outputs neither load nor drive the bus |
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lines significantly. The high-impedance state and |
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the increased drive provide the capability to drive |
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bus lines in bus-organized systems without need |
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for interface or pullup components. |
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OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ACT374 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ACT374 is characterized for operation from ±40°C to 85°C.
FUNCTION TABLE (each flip-flop)
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INPUTS |
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OUTPUT |
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Q |
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OE |
CLK |
D |
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L |
↑ |
H |
H |
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↑ |
L |
L |
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H or L |
X |
Q0 |
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H |
X |
X |
Z |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
SN54ACT374, SN74ACT374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS539E ± OCTOBER 1995 ± REVISED JANUARY 2000
logic symbol² |
logic diagram (positive logic) |
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1 |
EN |
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OE |
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11 |
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CLK |
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C1 |
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3 |
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2 |
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1D |
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1D |
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1Q |
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4 |
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5 |
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2D |
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2Q |
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7 |
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6 |
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3D |
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3Q |
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8 |
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9 |
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4D |
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4Q |
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13 |
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12 |
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5D |
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5Q |
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14 |
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15 |
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6D |
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6Q |
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17 |
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16 |
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7D |
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7Q |
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18 |
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19 |
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8D |
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8Q |
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OE |
1 |
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CLK |
11 |
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C1 |
2 |
1D |
3 |
1Q |
1D |
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To Seven Other Channels |
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²This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . ±0.5 V to 7 |
V |
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.5 V to VCC + 0.5 |
V |
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.5 V to VCC + 0.5 |
V |
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±20 mA |
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Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±20 mA |
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Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±50 mA |
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Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . ±200 mA |
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Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . 70°C/W |
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DW package . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . 58°C/W |
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N package . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . 69°C/W |
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PW package . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . 83°C/W |
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Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . ±65°C to 150°C |
³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |