Texas Instruments SN74ABTH18646APM, SN74ABTH182646APM, SNJ54ABTH18646AHV Datasheet

SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS

SCBS166D ± AUGUST 1993 ± REVISED JULY 1996

DMembers of the Texas Instruments SCOPE Family of Testability Products

DMembers of the Texas Instruments

Widebus Family

DCompatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture

DInclude D-Type Flip-Flops and Control Circuitry to Provide Multiplexed Transmission of Stored and Real-Time Data

DBus Hold on Data Inputs Eliminates the Need for External Pullup Resistors

DB-Port Outputs of 'ABTH182646A Devices Have Equivalent 25-Ω Series Resistors, So

No External Resistors Are Required

D State-of-the-Art EPIC-ΙΙB BiCMOS Design

DOne Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency

DSCOPE Instruction Set

±IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ

±Parallel-Signature Analysis at Inputs

±Pseudo-Random Pattern Generation From Outputs

±Sample Inputs/Toggle Outputs

±Binary Count From Outputs

±Device Identification

±Even-Parity Opcodes

DPackaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

SN54ABTH18646A, SN54ABTH182646A . . . HV PACKAGE

(TOP VIEW)

			1A2				1OE		GND			1SAB		1CLKAB		TDO		V		NC		TMS		1CLKBA		1SBA 1DIR GND						1B1		1B2		1B3
					1A1
																		CC
1A3		9			8		7		6		5			4		3		2		1		68 67 66 65 64 63 62 61																		1B4
		10																																		60
1A4		11																																		59				1B5
1A5		12																																		58				1B6
GND		13																																		57				GND
1A6		14																																		56				1B7
1A7		15																																		55				1B8
1A8		16																																		54				1B9
1A9		17																																		53				VCC
NC		18																																		52				NC
VCC		19																																		51				2B1
2A1		20																																		50				2B2
2A2		21																																		49				2B3
2A3		22																																		48				2B4
GND		23																																		47				GND
2A4		24																																		46				2B5
2A5		25																																		45				2B6
2A6		26																																		44				2B7
		27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
			2A7		2A8		2A9		GND			2OE		2SAB		2CLKAB		TDI		NC		CC		TCK		2CLKBA 2SBA GND						2DIR		2B9		2B8
																						V

NC ± No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE, Widebus, and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1996, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

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1

SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH

18-BIT TRANSCEIVERS AND REGISTERS

SCBS166D ± AUGUST 1993 ± REVISED JULY 1996

SN74ABTH18646A, SN74ABTH182646A . . . PM PACKAGE

1SAB 1CLKAB

(TOP VIEW)

1A2 1A1

1OE GND

TDO V TMS 1CLKBA 1SBA 1DIR GND 1B1 1B2 1B3

CC

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1A3 1

1A4 2

1A5 3 GND 4 1A6 5 1A7 6 1A8 7 1A9 8

VCC 9

2A1 10

2A2 11

2A3 12 GND 13 2A4 14 2A5 15 2A6 16

17 18 19

2A7

2A8

2A9

20 21 22 23

GND 2OE 2SAB 2CLKAB

24 25 26 27 28

TDI	CC	TCK	2CLKBA 2SBA
	V

48 1B4

47 1B5

46 1B6

45 GND

44 1B7

43 1B8

42 1B9

41 VCC

40 2B1

39 2B2

38 2B3

37 2B4

36 GND

35 2B5

34 2B6

33 2B7

29 30 31 32

GND 2DIR 2B9 2B8

description

The 'ABTH18646A and 'ABTH182646A scan test devices with 18-bit bus transceivers and registers are members of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed transmission of data directly from the input bus or from the internal registers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers and registers.

Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating both buses.

Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB and SAB, respectively. Figure 1 shows the four fundamental bus-management functions that are performed with the 'ABTH18646A and 'ABTH182646A.

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SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS

SCBS166D ± AUGUST 1993 ± REVISED JULY 1996

description (continued)

In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count addressing scheme is useful.

Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.

The B-port outputs of 'ABTH182646A, which are designed to source or sink up to 12 mA, include 25-Ω series resistors to reduce overshoot and undershoot.

The SN54ABTH18646A and SN54ABTH182646A are characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABTH18646A and SN74ABTH182646A are characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (normal mode, each 9-bit section)

				INPUTS				DATA I/O		OPERATION OR FUNCTION
	OE		DIR	CLKAB	CLKBA	SAB	SBA	A1 ± A9	B1 ± B9
		X	X	↑	X	X	X	Input	Unspecified²	Store A, B unspecified²
		X	X	X	↑	X	X	Unspecified²	Input	Store B, A unspecified²
		H	X	↑	↑	X	X	Input	Input	Store A and B data
		H	X	L	L	X	X	Input disabled	Input disabled	Isolation, hold storage
		L	L	X	X	X	L	Output	Input	Real-time B data to A bus
		L	L	X	X	X	H	Output	Input disabled	Stored B data to A bus
		L	H	X	X	L	X	Input	Output	Real-time A data to B bus
		L	H	X	X	H	X	Input disabled	Output	Stored A data to B bus

²The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs.

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SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH

18-BIT TRANSCEIVERS AND REGISTERS

SCBS166D ± AUGUST 1993 ± REVISED JULY 1996

BUS A

BUS B

BUS A

BUS B

OE	DIR	CLKAB CLKBA		SAB	SBA	OE	DIR	CLKAB	CLKBA	SAB	SBA
L	L	X	X	X	L	L	H	X	X	L	X
	REAL-TIME TRANSFER							REAL-TIME TRANSFER
		BUS B TO BUS A						BUS A TO BUS B

BUS A

BUS B

BUS A

BUS B

OE	DIR	CLKAB CLKBA		SAB	SBA	OE	DIR	CLKAB	CLKBA	SAB	SBA
X	X	↑	X	X	X	L	L	X	X	X	H
X	X	X	↑	X	X	L	H	X	X	H	X
H	X	↑	↑	X	X
		STORAGE FROM					TRANSFER STORED DATA
		A, B, OR A AND B						TO A AND/OR B

Figure 1. Bus-Management Functions

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SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS

SCBS166D ± AUGUST 1993 ± REVISED JULY 1996

functional block diagram

VCC	Boundary-Scan Register
1OE 62
53
1DIR
1CLKBA 55
1SBA 54
1CLKAB 59
60
1SAB
	C1
	1D
1A1 63	C1	51	1B1
	1D
	One of Nine Channels
VCC
2OE 21
2DIR 30
27
2CLKBA
2SBA 28
2CLKAB 23
22
2SAB
	C1
	1D
2A1 10	C1	40	2B1
	1D
	One of Nine Channels

	Bypass Register
	Boundary-Control
	Register
	Identification
	Register
VCC	58	TDO
TDI 24	Instruction
VCC	Register
TMS 56	TAP
26
	Controller
TCK

Pin numbers shown are for the PM package.

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SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH

18-BIT TRANSCEIVERS AND REGISTERS

SCBS166D ± AUGUST 1993 ± REVISED JULY 1996

						Terminal Functions
	TERMINAL NAME					DESCRIPTION
	1A1±1A9,					Normal-function A-bus I/O ports. See function table for normal-mode logic.
	2A1±2A9
	1B1±1B9,					Normal-function B-bus I/O ports. See function table for normal-mode logic.
	2B1±2B9
	1CLKAB, 1CLKBA,					Normal-function clock inputs. See function table for normal-mode logic.
	2CLKAB, 2CLKBA
	1DIR, 2DIR					Normal-function direction controls. See function table for normal-mode logic.
		GND				Ground
						Normal-function output enables. See function table for normal-mode logic. An internal pullup at each terminal forces the
	1OE, 2OE
						terminal to a high level if left unconnected.
	1SAB, 1SBA,					Normal-function select controls. See function table for normal-mode logic.
	2SAB, 2SBA
		TCK				Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous
						to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.
		TDI				Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data
						through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
		TDO				Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
						through the instruction register or selected data register.
		TMS				Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP
						controller states. An internal pullup forces TMS to a high level if left unconnected.
		VCC				Supply voltage

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SCBS166D ± AUGUST 1993 ± REVISED JULY 1996

test architecture

Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard 1149.1-1990. All test instructions, test data, and test control signals are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, TCK and TMS. The function of the TAP controller is to extract the synchronization (TCK) and state control (TMS) signals from the test bus and generate the appropriate on-chip control signals for the test structures in the device. Figure 2 shows the TAP-controller state diagram.

The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully one-half of the TCK cycle.

The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the device contains an 8-bit instruction register and four test-data registers: a 52-bit boundary-scan register, a 3-bit boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register.

Test-Logic-Reset

TMS = H	TMS = L

Run-Test/Idle

TMS = L

TMS = H	TMS = H		TMS = H
Select-DR-Scan			Select-IR-Scan
TMS = L			TMS = L
	TMS = H	TMS = H

Capture-DR	Capture-IR
TMS = L	TMS = L
Shift-DR	Shift-IR

TMS = L			TMS = L
	TMS = H		TMS = H
TMS = H			TMS = H
Exit1-DR		Exit1-IR
	TMS = L		TMS = L
Pause-DR		Pause-IR
TMS = L			TMS = L
	TMS = H		TMS = H
	TMS = L	TMS = L
Exit2-DR		Exit2-IR
	TMS = H		TMS = H
Update-DR		Update-IR
TMS = H	TMS = L	TMS = H	TMS = L

Figure 2. TAP-Controller State Diagram

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SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH

18-BIT TRANSCEIVERS AND REGISTERS

SCBS166D ± AUGUST 1993 ± REVISED JULY 1996

state diagram description

The TAP controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram shown in Figure 2 is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK.

As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers also can be reset to their power-up values.

The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left unconnected or if a board defect causes it to be open circuited.

For the 'ABTH18646A and 'ABTH182646A, the instruction register is reset to the binary value 10000001, which selects the IDCODE instruction. Bits 51±48 in the boundary-scan register are reset to logic 0, ensuring that these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at high-impedance state). Reset values of other bits in the boundary-scan register should be considered indeterminate. The boundary-control register is reset to the binary value 010, which selects the PSA test operation.

Run-Test/Idle

The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test operations. The Run-Test/Idle state also can be entered following-data register or instruction-register scans. Run-Test/Idle is provided as a stable state in which the test logic can be actively running a test or can be idle. The test operations selected by the boundary-control register are performed while the TAP controller is in the Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits either of these states on the next TCK cycle. These states allow the selection of either data-register scan or instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR state, the selected data register can capture a data value as specified by the current instruction. Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the Capture-DR state.

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the selected data register.

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SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS

SCBS166D ± AUGUST 1993 ± REVISED JULY 1996

Shift-DR (continued)

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain indefinitely. The Pause-DR state can suspend and resume data register-scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, such update occurs on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In the Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state. For the 'ABTH18646A and 'ABTH182646A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs during the TCK cycle, in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely. The Pause-IR state can suspend and resume instruction-register scan operations without loss of data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK, following entry to the Update-IR state.

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SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH

18-BIT TRANSCEIVERS AND REGISTERS

SCBS166D ± AUGUST 1993 ± REVISED JULY 1996

register overview

With the exception of the bypass and device-identification registers, any test register can be thought of as a serial-shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the four data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

Table 3 lists the instructions supported by the 'ABTH18646A and 'ABTH182646A. The even-parity feature specified for SCOPE devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are defined for SCOPE devices but are not supported by this device default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 3.

		Bit 7							Bit 0
	TDI	Parity	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1		TDO
									(LSB)
		(MSB)

Figure 3. Instruction Register Order of Scan

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SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS

SCBS166D ± AUGUST 1993 ± REVISED JULY 1996

data register description

boundary-scan register

The boundary-scan register (BSR) is 52 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin, one BSC for each normal-function I/O pin (one single cell for both input data and output data), and one BSC for each of the internally decoded output-enable signals (1OEA, 2OEA, 1OEB, 2OEB). The BSR is used 1) to store test data that is to be applied externally to the device output pins, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input pins.

The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or in Test-Logic-Reset, BSCs 51±48 are reset to logic 0, ensuring that these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at high-impedance state). Reset values of other BSCs should be considered indeterminate.

When external data is to be captured, the BSCs for signals 1OEA, 2OEA, 1OEB, and 2OEB capture logic values determined by the following positive-logic equations: 1OEA = 1OE •1DIR, 2OEA = 2OE •2DIR, 1OEB = 1OE •DIR, and 2OEB = 2OE •DIR. When data is to be applied externally, these BSCs control the drive state (active or high impedance) of their respective outputs.

The BSR order of scan is from TDI through bits 51±0 to TDO. Table 1 shows the BSR bits and their associated device pin signals.

Table 1. Boundary-Scan Register Configuration

BSR BIT	DEVICE			BSR BIT	DEVICE	BSR BIT	DEVICE
NUMBER	SIGNAL			NUMBER	SIGNAL	NUMBER	SIGNAL
51	2OEB			35	2A9-I/O	17	2B9-I/O
50	1OEB			34	2A8-I/O	16	2B8-I/O
49	2OEA			33	2A7-I/O	15	2B7-I/O
48	1OEA			32	2A6-I/O	14	2B6-I/O
47	2DIR			31	2A5-I/O	13	2B5-I/O
46	1DIR			30	2A4-I/O	12	2B4-I/O
45				29	2A3-I/O	11	2B3-I/O
	2OE
44				28	2A2-I/O	10	2B2-I/O
	1OE
43	2CLKAB			27	2A1-I/O	9	2B1-I/O
42	1CLKAB			26	1A9-I/O	8	1B9-I/O
41	2CLKBA			25	1A8-I/O	7	1B8-I/O
40	1CLKBA			24	1A7-I/O	6	1B7-I/O
39	2SAB			23	1A6-I/O	5	1B6-I/O
38	1SAB			22	1A5-I/O	4	1B5-I/O
37	2SBA			21	1A4-I/O	3	1B4-I/O
36	1SBA			20	1A3-I/O	2	1B3-I/O
				19	1A2-I/O	1	1B2-I/O
				18	1A1-I/O	0	1B1-I/O

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

11

SN54ABTH18646A, SN54ABTH182646A, SN74ABTH18646A, SN74ABTH182646A SCAN TEST DEVICES WITH

18-BIT TRANSCEIVERS AND REGISTERS

SCBS166D ± AUGUST 1993 ± REVISED JULY 1996

boundary-control register

The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run test (RUNT) instruction to implement additional test operations not included in the basic SCOPE instruction set. Such operations include PRPG, PSA, and binary count up (COUNT). Table 4 shows the test operations that are decoded by the BCR.

During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is reset to the binary value 010, which selects the PSA test operation. The BCR order of scan is shown in Figure 4.

	TDI	Bit 2	Bit 1	Bit 0	TDO
		(MSB)		(LSB)

Figure 4. Boundary-Control Register Order of Scan

bypass register

The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path, reducing the number of bits per test pattern that must be applied to complete a test operation. During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 5.

TDI

Bit 0

TDO

Figure 5. Bypass Register Order of Scan

12	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265