Texas Instruments SN74AC534DBLE, SN74AC534DBR, SN74AC534DW, SN74AC534DWR, SN74AC534N Datasheet

SN54AC534, SN74AC534

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS554A ± NOVEMBER 1995 ± REVISED MAY 1996

D 3-State Inverting Outputs Drive Bus Lines

SN54AC534 . . . J OR W PACKAGE

Directly

SN74AC534 . . . DB, DW, N, OR PW PACKAGE

D Full Parallel Access for Loading

(TOP VIEW)

D EPIC (Enhanced-Performance Implanted

1

20

VCC

OE

CMOS) 1- m Process

8Q

1Q

2

19

D Package Options Include Plastic

1D

3

18

8D

Small-Outline (DW), Shrink Small-Outline

2D

4

17

7D

(DB), Thin Shrink Small-Outline (PW),

2Q

5

16

7Q

Ceramic Chip Carriers (FK) and

3Q

6

15

6Q

Flatpacks (W), and Standard Plastic (N) and

3D

7

14

6D

Ceramic (J) DIPs

4D

8

13

5D

description

4Q

9

12

5Q

GND

10

11

CLK

These octal edge-triggered D-type flip-flops

SN54AC534 . . . FK PACKAGE

feature 3-state outputs designed specifically for

(TOP VIEW)

driving highly capacitive or relatively low-imped-

ance loads. The devices are particularly suitable

1D

1Q

OE

CC

8Q

for implementing buffer registers, I/O ports,

V

bidirectional bus drivers, and working registers.

3

2

1

20 19

8D

On the positive transition of the clock (CLK) input,

2D

4

18

7D

2Q

5

17

the Q outputs are set to the complements of the

3Q

6

16

7Q

logic levels set up at the data (D) inputs.

15

3D

7

6Q

A buffered output-enable

(OE)

input can be used

4D

8

14

6D

9

10 11

12 13

to place the eight outputs in either a normal logic

state (high or low logic levels) or a high-impedance

4Q

GND

CLK

5Q

5D

state. In the high-impedance state, the outputs

neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54AC534 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74AC534 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (each flip-flop)

			INPUTS		OUTPUT
			CLK	D		Q
	OE
	L		↑	H		L
	L		↑	L		H
	L		H or L	X
						Q	0
	H		X	X		Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1996, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN54AC534, SN74AC534

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS554A ± NOVEMBER 1995 ± REVISED MAY 1996

logic symbol²

logic diagram (positive logic)

1	EN
OE
11	C1
CLK
3	1D	1	2
1D			1Q
4			5
2D			2Q
7			6
3D			3Q
8			9
4D			4Q
13			12
5D			5Q
14			15
6D			6Q
17			16
7D			7Q
18			19
8D			8Q

OE	1
LE	11
		C1	2	1Q
	3
1D		1D
		To Seven Other Channels

²This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . ±200 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . .	. . . . . . . . . . . . . 0.6 W
DW package . . . . .	. . . . . . . . . . . . . 1.6 W
N package . . . . . . .	. . . . . . . . . . . . . 1.3 W
PW package . . . . .	. . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . ±65°C to 150°C

³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2.The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265