Texas Instruments SN74ABT8952DL, SN74ABT8952DLR, SN74ABT8952DW, SN74ABT8952DWR Datasheet

SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D ± AUGUST 1992 ± REVISED JULY 1996

D Members of the Texas Instruments

SN54ABT8952 . . . JT PACKAGE

SCOPE Family of Testability Products

SN74ABT8952 . . . DL OR DW PACKAGE

D Compatible With the IEEE Standard

(TOP VIEW)

1149.1-1990 (JTAG) Test Access Port and

CLKAB

CLKBA

1

28

Boundary-Scan Architecture

CLKENAB

2

27

CLKENBA

D Functionally Equivalent to 'BCT2952 and

OEAB

3

26

OEBA

'ABT2952 in the Normal-Function Mode

A1

B1

4

25

SCOPE Instruction Set

D

A2

B2

5

24

D IEEE Standard 1149.1-1990 Required

A3

6

23

B3

Instructions, Optional INTEST, CLAMP, and

GND

7

22

B4

HIGHZ

A4

8

21

VCC

D Parallel-Signature Analysis at Inputs With

A5

9

20

B5

Masking Option

A6

10

19

B6

D Pseudo-Random Pattern Generation From

A7

11

18

B7

A8

12

17

B8

Outputs

TDO

TDI

13

16

D

Sample Inputs/Toggle Outputs

TMS

TCK

14

15

DBinary Count From Outputs

DEven-Parity Opcodes

D Two Boundary-Scan Cells Per I/O for		SN54ABT8952 . . . FK PACKAGE
				(TOP VIEW)
	Greater Flexibility
							CC
	State-of-the-Art EPIC-ΙΙB BiCMOS Design		B1	B2	B3	B4		B5	B6
D							V
	Significantly Reduces Power Dissipation		4	3	2	1	28	27 26
D Package Options Include Shrink										B7
		OEBA	5						25
	Small-Outline (DL) and Plastic	CLKENBA	6						24	B8
	Small-Outline (DW) Packages, Ceramic	CLKBA	7						23	TDI
	Chip Carriers (FK), and Standard Ceramic	CLKAB	8						22	TCK
	DIPs (JT)	CLKENAB	9						21	TMS
description		OEAB	10						20	TDO
		A1	11						19	A8
	The 'ABT8952 scan test devices with octal		12 13 14 15 16 17 18
			A2	A3	GND	A4	A5	A6	A7
	registered bus transceivers are members of the
	Texas Instruments SCOPE testability integra-
	ted-circuit family. This family of devices supports
	IEEE Standard 1149.1-1990 boundary scan to
	facilitate testing of complex circuit-board assem-
	blies. Scan access to the test circuitry is
	accomplished via the 4-wire test access port
	(TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'BCT2952 and 'ABT2952 octal registered bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPE octal registered bus transceivers.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1996, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D ± AUGUST 1992 ± REVISED JULY 1996

description (continued)

Data flow in each direction is controlled by clock (CLKAB and CLKBA), clock-enable (CLKENAB and CLKENBA), and output-enable (OEAB and OEBA) inputs. For A-to-B data flow, A-bus data is stored in the associated registers on the low-to-high transition of CLKAB, provided that CLKENAB is low. Otherwise, if CLKENAB is high or CLKAB remains at a static low or high level, the register contents are not changed. When OEAB is low, the B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. Control for B-to-A data flow is similar to that for A-to-B, but uses CLKBA, CLKENBA, and OEBA.

In the test mode, the normal operation of the SCOPE registered bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.

Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT8952 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT8952 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE² (normal mode, each register)

			INPUTS			OUTPUT
				CLKAB	A	B
	OEAB		CLKENAB
	L		L	↑	L	L
	L		L	↑	H	H
	L		H	X	X	B0
	L		X	L	X	B0
	H		X	X	X	Z

²A-to-B data flow is shown; B-to-A data flow is similar but uses OEBA, CLKENBA, and CLKBA.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D ± AUGUST 1992 ± REVISED JULY 1996

functional block diagram

		Boundary-Scan Register
OEBA 26
CLKENBA 27
CLKBA 28
OEAB 3
CLKENAB 2
CLKAB 1
	MUX		C1
	G1		1D
	1
	1
A1 4					25	B1
			C1	MUX
			1D		G1
					1
					1
		One of Eight Channels
		Bypass Register
		Boundary-Control
			Register
VCC					13	TDO
TDI 16
		Instruction Register
VCC
14
TMS
	TAP
15	Controller
TCK

Pin numbers shown are for the DL, DW, and JT packages.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D ± AUGUST 1992 ± REVISED JULY 1996

								Terminal Functions
		TERMINAL						DESCRIPTION
		NAME
		A1±A8						Normal-function A-bus I/O ports. See function table for normal-mode logic.
		B1±B8						Normal-function B-bus I/O ports. See function table for normal-mode logic.
	CLKAB, CLKBA							Normal-function clock inputs. See function table for normal-mode logic.
								Normal-function clock-enable inputs. See function table for normal-mode logic.
	CLKENAB,				CLKENBA
		GND						Ground
								Normal-function output-enable inputs. See function table for normal-mode logic.
		OEAB,			OEBA
		TCK						Test clock. One of four pins required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous
								to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.
								Test data input. One of four pins required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data
		TDI						through the instruction register or selected data register. An internal pullup forces TDI to a high level if left
								unconnected.
		TDO						Test data output. One of four pins required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
								through the instruction register or selected data register.
		TMS						Test mode select. One of four pins required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP
								controller states. An internal pullup forces TMS to a high level if left unconnected.
		VCC						Supply voltage

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D ± AUGUST 1992 ± REVISED JULY 1996

test architecture

Serial-test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Standard 1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, namely TCK and TMS. The TAP controller extracts the synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully one-half of the TCK cycle.

The functional block diagram illustrates the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship among the test bus, the TAP controller, and the test registers. As illustrated, the device contains an 8-bit instruction register and three test-data registers: a 38-bit boundary-scan register, an 11-bit boundary-control register, and a 1-bit bypass register.

Test-Logic-Reset

TMS = H	TMS = L

Run-Test/Idle

TMS = L

TMS = H	TMS = H		TMS = H
Select-DR-Scan			Select-IR-Scan
TMS = L			TMS = L
	TMS = H	TMS = H

Capture-DR	Capture-IR
TMS = L	TMS = L
Shift-DR	Shift-IR

TMS = L			TMS = L
	TMS = H		TMS = H
TMS = H			TMS = H
Exit1-DR		Exit1-IR
	TMS = L		TMS = L
Pause-DR		Pause-IR
TMS = L			TMS = L
	TMS = H		TMS = H
	TMS = L	TMS = L
Exit2-DR		Exit2-IR
	TMS = H		TMS = H
Update-DR		Update-IR
TMS = H	TMS = L	TMS = H	TMS = L

Figure 1. TAP-Controller State Diagram

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D ± AUGUST 1992 ± REVISED JULY 1996

state diagram description

The TAP controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK.

As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. A stable state as a state the TAP controller can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers also can be reset to their power-up values.

The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left unconnected or if a board defect causes it to be open circuited.

For the 'ABT8952, the instruction register is reset to the binary value 11111111, which selects the BYPASS instruction. Each bit in the boundary-scan register is reset to logic 0 except bits 37±36, which are reset to logic 1. The boundary-control register is reset to the binary value 00000000010, which selects the PSA test operation with no input masking.

Run-Test/Idle

The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans. Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle.

The test operations selected by the boundary-control register are performed while the TAP controller is in the Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits either of these states on the next TCK cycle. These states allow the selection of either data-register scan or instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR state, the selected data register can capture a data value as specified by the current instruction. Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the Capture-DR state.

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the selected data register.

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D ± AUGUST 1992 ± REVISED JULY 1996

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.

On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, then such update occurs on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In the Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state.

For the 'ABT8952, the status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and, on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.

On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss of data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK, following entry to the Update-IR state.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

7

SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D ± AUGUST 1992 ± REVISED JULY 1996

register overview

With the exception of the bypass register, any test register can be thought of as a serial-shift register with a shadow latch on each bit. The bypass register differs in that it contains only a shift register. During the appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the three data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

Table 3 lists the instructions supported by the 'ABT8952. The even-parity feature specified for SCOPE devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are defined for SCOPE devices but are not supported by this device default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated, and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the binary value 11111111, which selects the BYPASS instruction. The IR order of scan is shown in Figure 2.

		Bit 7							Bit 0
	TDI	Parity	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1		TDO
									(LSB)
		(MSB)

Figure 2. Instruction Register Order of Scan

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265