Texas Instruments SN74ACT533DBLE, SN74ACT533DBR, SN74ACT533DW, SN74ACT533DWR, SN74ACT533N Datasheet

				SN54ACT533, SN74ACT533
	OCTAL TRANSPARENT D-TYPE LATCHES
					WITH 3-STATE OUTPUTS
	SCAS553B ± NOVEMBER 1995 ± REVISED JANUARY 2000
D Inputs Are TTL-Voltage Compatible	SN54ACT533 . . . J OR W PACKAGE
D 3-State Inverting Outputs Drive Bus Lines	SN74ACT533 . . . DB, DW, N, OR PW PACKAGE
					(TOP VIEW)
Directly
D EPIC (Enhanced-Performance Implanted					1	20	VCC
		OE
CMOS) 1- m Process
		1Q			2	19	8Q
D Package Options Include Plastic		1D			3	18	8D
Small-Outline (DW), Shrink Small-Outline		2D			4	17	7D
(DB), and Thin Shrink Small-Outline (PW)
		2Q			5	16	7Q
Packages, Ceramic Chip Carriers (FK) and
		3Q			6	15	6Q
Flatpacks (W), and Standard Plastic (N) and		3D			7	14	6D
Ceramic (J) DIPs		4D			8	13	5D
description		4Q			9	12	5Q
	GND				10	11	LE

The 'ACT533 devices are octal transparent D-type latches with 3-state outputs. When the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverted levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

SN54ACT533 . . . FK PACKAGE

(TOP VIEW)

	1D	1Q		CC	8Q
			OE V
2D	3	2	1	20 19		8D
	4				18
2Q	5				17	7D
3Q	6				16	7Q
3D	7				15	6Q
4D	8	10 11			14	6D
	9			12 13
	4Q	GND	LE	5Q	5D

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54ACT533 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ACT533 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (each latch)

		INPUTS		OUTPUT
		LE	D		Q
	OE
	L	H	H		L
	L	H	L		H
	L	L	X
					Q	0
	H	X	X		Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2000, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN54ACT533, SN74ACT533

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCAS553B ± NOVEMBER 1995 ± REVISED JANUARY 2000

logic symbol²

logic diagram (positive logic)

	1			EN
OE
11
LE				C1
3								2
1D				1D		1			1Q
4								5
2D									2Q
7								6
3D									3Q
8								9
4D									4Q
13								12
5D									5Q
14								15
6D									6Q
17								16
7D									7Q
18								19
8D									8Q

1
OE
11
LE
	C1	2
3	1D	1Q
1D
	To Seven Other Channels

²This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 69°C/W
PW package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . ±65°C to 150°C

³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265