Texas Instruments SN74ABTH16823DLR, SN74ABTH16823DGGR, SN74ABTH16823DL Datasheet

	SN54ABTH16823, SN74ABTH16823
	18-BIT BUS-INTERFACE FLIP-FLOPS
						WITH 3-STATE OUTPUTS
			SCBS664B ± APRIL 1996 ± REVISED MAY 1997
D Members of the Texas Instruments	SN54ABTH16823 . . . WD PACKAGE
Widebus Family	SN74ABTH16823 . . . DGG OR DL PACKAGE
D State-of-the-Art EPIC-ΙΙB BiCMOS Design						(TOP VIEW)
Significantly Reduces Power Dissipation
	1CLR					1	56	1CLK
D ESD Protection Exceeds 2000 V Per
		1OE				2	55	1CLKEN
MIL-STD-883, Method 3015; Exceeds 200 V		1Q1				3	54	1D1
Using Machine Model (C = 200 pF, R = 0)	GND					4	53	GND
D Typical VOLP (Output Ground Bounce) < 1 V		1Q2				5	52	1D2
at VCC = 5 V, TA = 25°C		1Q3				6	51	1D3
D High-Impedance State During Power Up		VCC				7	50	VCC
and Power Down		1Q4				8	49	1D4
D Distributed VCC and GND Pin Configuration		1Q5				9	48	1D5
		1Q6				10	47	1D6
Minimizes High-Speed Switching Noise
	GND					11	46	GND
D Flow-Through Architecture Optimizes PCB
		1Q7				12	45	1D7
Layout
		1Q8				13	44	1D8
D High-Drive Outputs (±32-mA IOH, 64-mA IOL)
		1Q9				14	43	1D9
D Bus Hold on Data Inputs Eliminates the		2Q1				15	42	2D1
Need for External Pullup/Pulldown		2Q2				16	41	2D2
Resistors		2Q3				17	40	2D3
D Package Options Include Plastic 300-mil	GND					18	39	GND
		2Q4				19	38	2D4
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil		2Q5				20	37	2D5
Fine-Pitch Ceramic Flat (WD) Package		2Q6				21	36	2D6
Using 25-mil Center-to-Center Spacings		VCC				22	35	VCC
		2Q7				23	34	2D7
description		2Q8				24	33	2D8
These 18-bit flip-flops feature 3-state outputs	GND					25	32	GND
		2Q9				26	31	2D9
designed specifically for driving highly capacitive
		2OE				27	30	2CLKEN
or relatively low-impedance loads. They are
	2CLR					28	29	2CLK
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.

The 'ABTH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock.

A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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SN54ABTH16823, SN74ABTH16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SCBS664B ± APRIL 1996 ± REVISED MAY 1997

description (continued)

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54ABTH16823 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABTH16823 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (each 9-bit flip-flop)

				INPUTS					OUTPUT
									Q
	OE	CLR			CLKEN		CLK	D
	L		L		X		X	X	L
	L		H		L		↑	H	H
	L		H		L		↑	L	L
	L		H		L		L	X	Q0
	L		H		H		X	X	Q0
	H		X		X		X	X	Z

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABTH16823, SN74ABTH16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SCBS664B ± APRIL 1996 ± REVISED MAY 1997

logic symbol²

				2
		1OE				EN1
				1		R2
	1CLR
				55		G3
	1CLKEN
56							3C4
	1CLK
				27		EN5
		2OE
				28		R6
		2CLR
				30
						G7
2CLKEN
29							7C8
	2CLK
54										3
		1D1				4D		1, 2			1Q1
52										5
		1D2									1Q2
51										6
		1D3									1Q3
										8
49											1Q4
		1D4
										9
48											1Q5
		1D5
										10
47											1Q6
		1D6
										12
45											1Q7
		1D7
										13
44											1Q8
		1D8
43										14
		1D9									1Q9
42										15
		2D1				8D		5, 6			2Q1
										16
41											2Q2
		2D2
40										17
		2D3									2Q3
										19
38											2Q4
		2D4
										20
37											2Q5
		2D5
										21
36											2Q6
		2D6
34										23
		2D7									2Q7
33										24
		2D8									2Q8
31										26
		2D9									2Q9

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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