Texas Instruments SN74ABT125D, SN74ABT125DBLE, SN74ABT125DBR, SN74ABT125DR, SN74ABT125N Datasheet

SN54ABT125, SN74ABT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

	SCBS182E ± FEBRUARY 1997 ± REVISED MAY 1997
D State-of-the-Art EPIC-ΙΙB BiCMOS Design	SN54ABT125 . . . J OR W PACKAGE
Significantly Reduces Power Dissipation	SN74ABT125 . . . D, DB, N, OR PW PACKAGE
	(TOP VIEW)

DESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V							VCC
	1OE				1	14
Using Machine Model (C = 200 pF, R = 0)		1A			2	13	4OE
D Latch-Up Performance Exceeds 500 mA Per		1Y					4A
					3	12
JEDEC Standard JESD-17							4Y
	2OE				4	11
D Typical VOLP (Output Ground Bounce) < 1 V		2A
					5	10	3OE
at VCC = 5 V, TA = 25°C		2Y			6	9	3A
D High-Impedance State During Power Up	GND				7	8	3Y
and Power Down
D High-Drive Outputs (±32-mA IOH, 64-mA IOL)	SN54ABT125 . . . FK PACKAGE

D Package Options Include Plastic		(TOP VIEW)
		1A	1OE	NC	V	4OE
Small-Outline (D), Shrink Small-Outline
					CC
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),	1Y	3	2	1	20 19		4A
Ceramic Flat (W) Package, and Plastic (N)		4				18
and Ceramic (J) DIPs	NC	5				17	NC
	2OE	6				16	4Y
description	NC	7				15	NC
The 'ABT125 quadruple bus buffer gates feature	2A	8				14	3OE
		9	10 11 12 13
independent line drivers with 3-state outputs.		2Y	GND	NC	3Y	3A
Each output is disabled when the associated
output-enable (OE) input is high.	NC ± No internal connection

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT125 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT125 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (each buffer)

	INPUTS		OUTPUT
		A	Y
	OE
	L	H	H
	L	L	L
	H	X	Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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SN54ABT125, SN74ABT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCBS182E ± FEBRUARY 1997 ± REVISED MAY 1997

logic symbol²

				1	EN	1
	1OE							3
				2					1Y
		1A
				4				6
	2OE
				5					2Y
		2A
				10
	3OE							8
				9					3Y
		3A
				13				11
	4OE
				12					4Y
		4A
	² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
	Pin numbers shown are for the D, DB, J, N, PW, and W packages.

logic diagram (positive logic)

1OE	1		3OE	10
1A	2	3	3A	9	8
		1Y			3Y
2OE	4		4OE	13
2A	5	6	4A	12	11
		2Y			4Y

Pin numbers shown are for the D, DB, J, N, PW, and W packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . .	±0.5 V to 5.5	V
Current into any output in the low state, IO: SN54ABT125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 96 mA
SN74ABT125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 127°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 158°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 78°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 170°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±65°C to 150°C

³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stressratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2.The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABT125, SN74ABT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCBS182E ± FEBRUARY 1997 ± REVISED MAY 1997

recommended operating conditions (see Note 3)

			SN54ABT125		SN74ABT125		UNIT
			MIN	MAX	MIN	MAX
VCC		Supply voltage	4.5	5.5	4.5	5.5	V
VIH		High-level input voltage	2		2		V
VIL		Low-level input voltage		0.8		0.8	V
VI		Input voltage	0	VCC	0	VCC	V
IOH		High-level output current		±24		±32	mA
IOL		Low-level output current		48		64	mA
t/	v	Input transition rise or fall rate		10		10	ns/V
t/	VCC	Power-up ramp rate	200		200		µs/V
TA		Operating free-air temperature	±55	125	±40	85	°C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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