Texas Instruments SN74ABT3612-15PCB, SN74ABT3612-15PQ, SN74ABT3612-20PCB, SN74ABT3612-20PQ, SN74ABT3612-30PCB Datasheet

SN74ABT3612 64 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS129G ± JULY 1992 ± REVISED APRIL 1998

DFree-Running CLKA and CLKB Can Be Asynchronous or Coincident

DTwo Independent 64 × 36 Clocked FIFOs

Buffering Data in Opposite Directions

DMailbox-Bypass Register for Each FIFO

DProgrammable Almost-Full and Almost-Empty Flags

DMicroprocessor Interface Control Logic

DEFA, FFA, AEA, and AFA Flags Synchronized by CLKA

description

DEFB, FFB, AEB, and AFB Flags Synchronized by CLKB

DPassive Parity Checking on Each Port

DParity Generation Can Be Selected for Each Port

DLow-Power Advanced BiCMOS Technology

DSupports Clock Frequencies up to 67 MHz

DFast Access Times of 10 ns

DPackage Options Include 120-Pin Thin Quad Flat (PCB) and 132-Pin Plastic Quad Flat (PQ) Packages

The SN74ABT3612 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10 ns. Two independent 64 ×36 dual-port SRAM FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost-full and almost-empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider datapaths.

The SN74ABT3612 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The full flag (FFA, FFB) and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The empty flag (EFA, EFB) and almost-empty (AEA, AEB) flag of a FIFO are two-stage synchronized to the port clock that reads data from its array.

The SN74ABT3612 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the following application reports:

DFIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007)

DParity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications (literature number SCAA015)

DMetastability Performance of Clocked FIFOs (literature number SCZA004)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1998, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN74ABT3612 64 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS129G ± JULY 1992 ± REVISED APRIL 1998

PCB PACKAGE (TOP VIEW)

				A24		A25		A26			CC		A27		A28		A29			GND A30					A31		A32		A33		A34			A35			GND		B35			B34		B33			B32		B31			B30		GND B29				B28			B27				CC		B26			B25			B24			B23
										V																																																						V
				120		119		118		117			116		115		114		113		112			111			110		109		108		107			106			105		104			103		102			101		100			99		98		97			96			95			94			93			92			91
	A23			1																																																																								90
	A22			2																																																																								89
	A21			3																																																																								88
GND				4																																																																								87
	A20			5																																																																								86
	A19			6																																																																								85
	A18			7																																																																								84
	A17			8																																																																								83
	A16			9																																																																								82
	A15			10																																																																								81
	A14			11																																																																								80
	A13			12																																																																								79
	A12			13																																																																								78
	A11			14																																																																								77
	A10			15																																																																								76
GND				16																																																																								75
	A9			17																																																																								74
	A8			18																																																																								73
	A7			19																																																																								72
VCC				20																																																																								71
	A6			21																																																																								70
	A5			22																																																																								69
	A4			23																																																																								68
	A3			24																																																																								67
GND				25																																																																								66
	A2			26																																																																								65
	A1			27																																																																								64
	A0			28																																																																								63
	EFA			29																																																																								62
AEA				30																																																																								61
				31		32		33		34			35		36		37		38		39			40			41		42		43		44			45			46		47			48		49			50		51			52		53		54			55			56			57			58			59			60

B22

B21 GND B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 GND B9 B8 B7

VCC

B6

B5

B4

B3 GND B2 B1 B0

EFB AEB AFB

AFA

FFA

CSA ENA CLKA W/RA

V

PGA

PEFA

MBF2 MBA FS1 FS0

ODD/EVEN

RST GND

NC NC NC NC MBB

MBF1

PEFB

PGB V

W/RB CLKB ENB

CSB

FFB

CC

CC

NC ± No internal connection

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ABT3612 64 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS129G ± JULY 1992 ± REVISED APRIL 1998

PQ PACKAGE² (TOP VIEW)

					AFA			FFA		CSA ENA				CLKA		W/RA		V		PGA		PEFA		GND			MBF2		MBA			FS1			FS0			ODD/EVEN			RST			GND			NC		NC		NC		NC		MBB			MBF1			GND			PEFB				PGB		V				W/RB		CLKB			ENB			CSB			FFB				AFB
																		CC																																																					CC
			17 16 15 14 13 12 11 10																			9		8			7		6			5			4		3				2			1 132					130						128						126						124						122						120					118
GND			18																																												131				129							127						125						123						121						119						117
																																																																																								116
AEA			19																																																																																					115
EFA			20																																																																																					114
A0			21																																																																																					113
A1			22																																																																																					112
A2			23																																																																																					111
GND			24																																																																																					110
A3			25																																																																																					109
A4			26																																																																																					108
A5			27																																																																																					107
A6			28																																																																																					106
VCC			29																																																																																					105
A7			30																																																																																					104
A8			31																																																																																					103
A9			32																																																																																					102
GND			33																																																																																					101
A10			34																																																																																					100
A11			35																																																																																					99
VCC			36																																																																																					98
A12			37																																																																																					97
A13			38																																																																																					96
A14			39																																																																																					95
GND			40																																																																																					94
A15			41																																																																																					93
A16			42																																																																																					92
A17			43																																																																																					91
A18			44																																																																																					90
A19			45																																																																																					89
A20			46																																																																																					88
GND			47																																																																																					87
A21			48																																																																																					86
A22			49																																																																																					85
A23			50																																																																																					84
			51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
					V			A24		A25 A26				GND		A27		A28		A29		V		A30			A31		A32			GND			A33			A34			A35			GND			B35		B34		B33		GND			B32		B31			B30			V			B29			B28				B27		GND			B26			B25			B24				V
						CC																CC																																											CC																								CC

NC ± No internal connection

² Uses Yamaichi socket IC51-1324-828

GND AEB EFB B0 B1 B2 GND B3 B4 B5 B6

VCC

B7

B8

B9 GND B10 B11

VCC

B12

B13

B14 GND B15 B16 B17 B18 B19 B20 GND B21 B22 B23

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SN74ABT3612 64 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS129G ± JULY 1992 ± REVISED APRIL 1998

functional block diagram

CLKA

CSA

W/RA

ENA

MBA

RST

ODD/

EVEN

FFA

AFA

FS0

FS1 A0 ± A35

EFA

AEA

PGA

PEFA

MBF2

Port-A

Control

Logic

Parity

Gen/Check

Mail1

Register

Device

Control

Input Register

64 × 36

SRAM

Write Read

Pointer Pointer

Parity

Generation

Output Register

		Status-Flag
		Logic
FIFO1
36
		Programmable-Flag
		Offset Register
FIFO2
		Status-Flag
		Logic
		Read	Write
OutputRegister		Pointer	Pointer
	Parity Generation	64	InputRegister
			× 36
		SRAM

Mail2

Register

Parity

Gen/Check

MBF1

PEFB

PGB

36

EFB

AEB

B0 ± B35

FFB

AFB

36

	CLKB
Port-B	CSB
Control	W/RB
Logic	ENB
	MBB

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ABT3612

64 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS129G ± JULY 1992 ± REVISED APRIL 1998

Terminal Functions

PIN NAME

I/O

DESCRIPTION

A0 ± A35

I/O

Port-A data. The 36-bit bidirectional data port for side A.

AEA

O

Port-A almost-empty flag. Programmable flag synchronized to CLKA.

AEA

is low when the number of words in FIFO2

(port A)

is less than or equal to the value in offset register X.

O

Port-B almost-empty flag. Programmable flag synchronized to CLKB.

is low when the number of words in FIFO1

AEB

AEB

(port B)

is less than or equal to the value in offset register X.

O

Port-A almost-full flag. Programmable flag synchronized to CLKA.

is low when the number of empty locations in

AFA

AFA

(port A)

FIFO1 is less than or equal to the value in offset register X.

O

Port-B almost-full flag. Programmable flag synchronized to CLKB.

is low when the number of empty locations in

AFB

AFB

(port B)

FIFO2 is less than or equal to the value in offset register X.

B0 ± B35

I/O

Port-B data. The 36-bit bidirectional data port for side B.

CLKA

I

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous

or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the low-to-high transition of CLKA.

CLKB

I

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous

or coincident to CLKA. EFB, FFB, AFB, and AEB are synchronized to the low-to-high transition of CLKB.

CSA

I

Port-A chip select.

CSA

must be low to enable a low-to-high transition of CLKA to read or write data on port A. The

A0 ± A35 outputs are in the high-impedance state when CSA is high.

Port-B chip select.

must be low to enable a low-to-high transition of CLKB to read or write data on port B. The

CSB

I

CSB

B0 ± B35 outputs are in the high-impedance state when CSB is high.

Port-A empty flag.

is synchronized to the low-to-high transition of CLKA. When

is low, FIFO2 is empty and

EFA

EFA

O

reads from its memory are disabled. Data can be read from FIFO2 to the output register when

EFA

is high. EFA is forced

EFA

(port A)

low when the device is reset and is set high by the second low-to-high transition of CLKA after data is loaded into empty

FIFO2 memory.

Port-B empty flag.

is synchronized to the low-to-high transition of CLKB. When

is low, FIFO1 is empty and

EFB

EFB

O

reads from its memory are disabled. Data can be read from FIFO1 to the output register when

EFB

is high.

EFB

is forced

EFB

(port B)

low when the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded into empty

FIFO1 memory.

ENA

I

Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.

ENB

I

Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.

Port-A full flag.

is synchronized to the low-to-high transition of CLKA. When

is low, FIFO1 is full and writes

O

FFA

FFA

FFA

to its memory are disabled. FFA is forced low when the device is reset and is set high by the second low-to-high

(port A)

transition of CLKA after reset.

O

Port-B full flag.

FFB

is synchronized to the low-to-high transition of CLKB. When

FFB

is low, FIFO2 is full and writes

FFB

to its memory are disabled. FFB is forced low when the device is reset and is set high by the second low-to-high

(port B)

transition of CLKB after reset.

Flag-offset selects. The low-to-high transition of

latches the values of FS0 and FS1, which selects one of four

FS1, FS0

I

RST

preset values for the almost-empty flag and almost-full flag offset.

Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the

MBA

I

A0 ± A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects

FIFO2 output register data for output.

Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the

MBB

I

B0 ± B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects

FIFO1 output register data for output.

Mail1 register flag.

MBF1

is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes

MBF1

O

to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B

read is selected and MBB is high. MBF1 is set high when the device is reset.

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SN74ABT3612 64 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS129G ± JULY 1992 ± REVISED APRIL 1998

Terminal Functions (Continued)

PIN NAME

I/O

DESCRIPTION

Mail2 register flag.

is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes

MBF2

MBF2

O

to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A

read is selected and MBA is high. MBF2 is set high when the device is reset.

is high and even parity is checked

ODD/

Odd/even parity select. Odd parity is checked on each port when ODD/EVEN

I

when ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is

EVEN

enabled for a read operation.

Port-A parity error flag. When any byte applied to A0 ± A35 fails parity,

is low. Bytes are organized as

PEFA

A0 ± A8, A9 ± A17, A18 ± A26, and A27 ± A35, with the most-significant bit of each byte serving as the parity bit.

PEFA

O

The type of parity checked is determined by the state of ODD/EVEN.

(port A)

The parity trees used to check the A0 ± A35 inputs are shared by the mail2 register to generate parity if parity

generation is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having W/RA low,

MBA high, and PGA high, PEFA is forced high regardless of the state of the A0 ± A35 inputs.

Port-B parity error flag. When any byte applied to terminals B0 ± B35 fails parity,

is low. Bytes are organized

PEFB

as B0 ± B8, B9 ± B17, B18 ± B26, and B27 ± B35, with the most-significant bit of each byte serving as the parity bit.

PEFB

O

The type of parity checked is determined by the state of ODD/EVEN.

(port B)

The parity trees used to check the B0 ± B35 inputs are shared by the mail1 register to generate parity if parity

generation is selected by PGB. Therefore, if a mail1 read with parity generation is set up by having W/RB low,

MBB high, and PGB high, PEFB is forced high regardless of the state of the B0 ± B35 inputs.

Port-A parity generation. Parity is generated for data reads from port A when PGA is high. The type of parity

PGA

I

generated is selected by the state of ODD/EVEN. Bytes are organized as A0 ± A8, A9 ± A17, A18 ± A26, and

A27± A35. The generated parity bits are output in the most-significant bit of each byte.

Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity

PGB

I

generated is selected by the state of ODD/EVEN. Bytes are organized as B0 ± B8, B9 ± B17, B18 ± B26, and

B27± B35. The generated parity bits are output in the most-significant bit of each byte.

Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must

RST

I

occur while RST is low. This sets AFA, AFB, MBF1, and MBF2 high and EFA,

EFB,

AEA,

AEB, FFA, and FFB low.

The low-to-high transition of RST latches the status of FS1 and FS0 to select almost-full flag and almost-empty

flag offset.

Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a

W/RA

I

low-to-high transition of CLKA. The A0 ± A35 outputs are in the high-impedance state when W/RA is high.

Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a

W/RB

I

low-to-high transition of CLKB. The B0 ± B35 outputs are in the high-impedance state when W/RB is high.

detailed description

reset

The SN74ABT3612 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. RST can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFB) low, the empty flags (EFA, EFB) low, the almost-empty flags (AEA, AEB) low, and the almost-full flags (AFA, AFB) high. A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FFA is set high after two low-to-high transitions of CLKA and FFB is set high after two low-to-high transitions of CLKB. The device must be reset after power up before data is written to its memory.

A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ABT3612 64 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS129G ± JULY 1992 ± REVISED APRIL 1998

reset (continued)

Table 1. Flag Programming

			ALMOST-FULL AND
FS1	FS0	RST	ALMOST-EMPTY FLAG
			OFFSET REGISTER (X)
H	H	↑	16
H	L	↑	12
L	H	↑	8
L	L	↑	4

FIFO write/read operation

The state of the port-A data (A0±A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0±A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0±A35 outputs are active when both CSA and W/RA are low. Data is loaded into FIFO1 from the A0±A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low, and FFA is high. Data is read from FIFO2 to the A0±A35 outputs by a low-to-high transition of CLKA when CSA is low, W/RA is low, ENA is high, MBA is low, and EFA is high (see Table 2).

Table 2. Port-A Enable Function Table

CSA	W/RA	ENA	MBA	CLKA	A0 ± A35 OUTPUTS	PORT FUNCTION
H	X	X	X	X	In high-impedance state	None
L	H	L	X	X	In high-impedance state	None
L	H	H	L	↑	In high-impedance state	FIFO1 write
L	H	H	H	↑	In high-impedance state	Mail1 write
L	L	L	L	X	Active, FIFO2 output register	None
L	L	H	L	↑	Active, FIFO2 output register	FIFO2 read
L	L	L	H	X	Active, mail2 register	None
				↑
L	L	H	H		Active, mail2 register	Mail2 read (set	MBF2	high)

The port-B control signals are identical to those of port A. The state of the port-B data (B0±B35) outputs is controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0±B35 outputs are in the high-impedance state when either CSB or W/RB is high. The B0±B35 outputs are active when both CSB and W/RB are low.

Data is loaded into FIFO2 from the B0±B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB is high, ENB is high, MBB is low, and FFB is high. Data is read from FIFO1 to the B0±B35 outputs by a low-to-high transition of CLKB when CSB is low, W/RB is low, ENB is high, MBB is high, and EFB is high (see Table 3).

The setupand hold-time constraints to the port clocks for the port-chip selects (CSA, CSB) and write/read selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select can change states during the setupand hold-time window of the cycle.

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7

SN74ABT3612 64 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS129G ± JULY 1992 ± REVISED APRIL 1998

FIFO write/read operation (continued)

Table 3. Port-B Enable Function Table

CSB	W/RB	ENB	MBB	CLKB	B0 ± B35 OUTPUTS	PORT FUNCTION
H	X	X	X	X	In high-impedance state	None
L	H	L	X	X	In high-impedance state	None
L	H	H	L	↑	In high-impedance state	FIFO2 write
L	H	H	H	↑	In high-impedance state	Mail2 write
L	L	L	L	X	Active, FIFO1 output register	None
L	L	H	L	↑	Active, FIFO1 output register	FIFO1 read
L	L	L	H	X	Active, mail1 register	None
				↑
L	L	H	H		Active, mail1 register	Mail1 read (set	MBF1	high)

synchronized FIFO flags

Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously to one another. EFA, AEA, FFA, and AFA are synchronized to CLKA. EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2.

Table 4. FIFO1 Flag Operation

	NUMBER OF WORDS	SYNCHRONIZED		SYNCHRONIZED
		TO CLKB		TO CLKA
	IN FIFO1²
		EFB	AEB	AFA	FFA
	0	L	L	H	H
	1 to X	H	L	H	H
	(X +1) to [64 ± (X +1)]	H	H	H	H
	(64 ± X) to 63	H	H	L	H
	64	H	H	L	L

² X is the value in the almost-empty flag and almost-full flag offset register.

Table 5. FIFO2 Flag Operation

	NUMBER OF WORDS	SYNCHRONIZED		SYNCHRONIZED
		TO CLKA		TO CLKB
	IN FIFO2²
		EFA	AEA	AFB	FFB
	0	L	L	H	H
	1 to X	H	L	H	H
	(X +1) to [64 ± (X +1)]	H	H	H	H
	(64 ± X) to 63	H	H	L	H
	64	H	H	L	L

² X is the value in the almost-empty flag and almost-full flag offset register.

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SN74ABT3612 64 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS129G ± JULY 1992 ± REVISED APRIL 1998

empty flags (EFA, EFB)

The empty flag of a FIFO is synchronized to the port clock that reads data from its array. When the empty flag is high, new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and attempted FIFO reads are ignored.

The read pointer of a FIFO is incremented each time a new word is clocked to the output register. A word written to a FIFO can be read to the FIFO output register in a minimum of three cycles of the empty flag synchronizing clock; therefore, an empty flag is low if a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The empty flag of the FIFO is set high by the second low-to-high transition of the synchronizing clock and the new data word can be read to the FIFO output register in the following cycle.

A low-to-high transition on an empty flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 6 and 7).

full flags (FFA, FFB)

The full flag of a FIFO is synchronized to the port clock that writes data to its array. When the full flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is low and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, the write pointer is incremented. From the time a word is read from a FIFO, the previous memory location is ready to be written in a minimum of three cycles of the full flag synchronizing clock; therefore, a full flag is low if less than two cycles of the full-flag synchronizing clock have elapsed since the next memory write location has been read. The second low-to-high transition on the full-flag synchronizing clock after the read sets the full flag high and data can be written in the following clock cycle.

A low-to-high transition on a full-flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 8 and 9).

almost-empty flags (AEA, AEB)

The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The almost-empty state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a device reset (see reset). An almost-empty flag is low when the FIFO contains X or less words in memory and is high when the FIFO contains (X + 1) or more words.

Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for the almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1) or more words remains low if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of the synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 11 and 12).

almost-full flags (AFA, AFB)

The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The almost-full state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a device reset (see reset). An almost-full flag is low when the FIFO contains (64

± X) or more words in memory and is high when the FIFO contains [64 ± (X + 1)] or less words.

Two low-to-high transitions of the almost-full flag synchronizing clock are required after a FIFO read for the almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [64 ± (X + 1)] or less words remains low if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of words in memory to [64 ± (X + 1)]. An almost-full flag is set high by the second low-to-high

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9

SN74ABT3612 64 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS129G ± JULY 1992 ± REVISED APRIL 1998

almost-full flags (AFA, AFB) (continued)

transition of the synchronizing clock after the FIFO read that reduces the number of words in memory to [64 ± (X + 1)]. A low-to-high transition of an almost-full flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after the read that reduces the number of words in memory to [64 ± (X + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 13 and 14).

mailbox registers

Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port-data-transfer operation. A low-to-high transition on CLKA writes A0±A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA and MBA is high. A low-to-high transition on CLKB writes B0±B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and MBB is high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while the mail flag is low.

When a port's data outputs are active, the data on the bus comes from the FIFO output register when the port mailbox-select input (MBA, MBB) is low and from the mail register when MBA/MBB is high. The mail1 register flag (MBF1) is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB and MBB is high. The mail2 register flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A read is selected by CSA, W/RA, and ENA and MBA is high. The data in a mail register remains intact after it is read and changes only when new data is written to the register.

parity checking

The port-A inputs (A0±A35) and port-B inputs (B0±B35) each have four parity trees to check the parity of incoming (or outgoing) data. A parity failure on one or more bytes of the input bus is reported by a low level on the port-parity-error flag (PEFA, PEFB). Oddor even-parity checking can be selected and the parity-error flags can be ignored if this feature is not desired.

Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select input. A parity error on one or more bytes of a port is reported by a low level on the corresponding PEFA, PEFB. Port-A bytes are arranged as A0±A8, A9±A17, A18±A26, and A27±A35, with the most-significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0±B8, B9±B17, B18±B26, and B27±B35, with the most-significant bit of each byte used as the parity bit. When odd/even parity is selected, PEFA, PEFB is low if any byte on the port has an odd/even number of low levels applied to the bits.

The four parity trees used to check the A0±A35 inputs are shared by the mail2 register when parity generation is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is selected with W/RA low, CSA low, ENA high, MBA high, and PGA high, PEFA is held high, regardless of the levels applied to the A0±A35 inputs. Likewise, the parity trees used to check the B0±B35 inputs are shared by the mail1 register when parity generation is selected for port-B reads (PGB = high). When a port-B read from the mail1 register with parity generation is selected with W/RB low, CSB low, ENB high, MBB high, and PGB high, PEFB is held high, regardless of the levels applied to the B0±B35 inputs.

parity generation

A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the SN74ABT3612 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged as A0±A8, A9±A17, A18±A26, and A27±A35, with the most-significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0±B8, B9±B17, B18±B26, and B27±B35, with the most-significant bit of each byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all 36 inputs, regardless of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the most-significant bits of each byte as the word is read to the data outputs.

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