Texas Instruments SN74ABT827DBLE, SN74ABT827DBR, SN74ABT827DW, SN74ABT827DWR, SN74ABT827NT Datasheet

SN54ABT827, SN74ABT827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

		SCBS159D ± JANUARY 1991 ± REVISED MAY 1997
D State-of-the-Art EPIC-ΙΙB BiCMOS Design	SN54ABT827 . . . JT PACKAGE
Significantly Reduces Power Dissipation	SN74ABT827 . . . DB, DW, NT, OR PW PACKAGE
D Flow-Through Architecture Optimizes PCB					(TOP VIEW)
Layout								VCC
		OE1			1	24
D Latch-Up Performance Exceeds 500 mA Per
		A1			2	23		Y1
JEDEC Standard JESD-17		A2			3	22		Y2
D Typical VOLP (Output Ground Bounce) < 1 V		A3			4	21		Y3
at VCC = 5 V, TA = 25°C		A4			5	20		Y4
		A5			6	19		Y5
D High-Impedance State During Power Up
		A6			7	18		Y6
and Power Down
		A7			8	17		Y7
D High-Drive Outputs (±32-mA IOH, 64-mA IOL)
		A8			9	16		Y8
D Package Options Include Plastic		A9			10	15		Y9
Small-Outline (DW), Shrink Small-Outline		A10			11	14		Y10
(DB), and Thin Shrink Small-Outline (PW)
	GND				12	13		OE2
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs	SN54ABT827 . . . FK PACKAGE
description					(TOP VIEW)

These 10-bit buffers or bus drivers provide a high-performance bus interface for wide data paths or buses carrying parity.

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all ten outputs are in the high-impedance state. The 'ABT827 provide true data at the outputs.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure

the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

	A2	A1	OE1	NC	CC	Y1	Y2
					V
A3	4	3	2	1	28	27 26		Y3
	5						25
A4	6						24	Y4
A5	7						23	Y5
NC	8						22	NC
A6	9						21	Y6
A7	10						20	Y7
A8	11						19	Y8
	12 13 14			15 16		17 18
	A9	A10	GND	NC	OE2	Y10	Y9

NC ± No internal connection

The SN54ABT827 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT827 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE

			INPUTS				OUTPUT
							Y
	OE1			OE2		A
	L			L		L	L
	L			L		H	H
	H			X		X	Z
	X			H		X	Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN54ABT827, SN74ABT827 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCBS159D ± JANUARY 1991 ± REVISED MAY 1997

logic symbol²											logic diagram (positive logic)
													1
		1			&						OE1
													13
OE1
		13					EN					OE2
	OE2								2										23
2									23			A1								Y1
	A1				1						Y1
3									22
	A2										Y2
4									21							To Nine Other Channels
	A3										Y3
5									20
	A4										Y4
6									19
	A5										Y5
7									18
	A6										Y6
8									17
	A7										Y7
									16
9											Y8
	A8
									15
10											Y9
	A9
										14
11											Y10
	A10

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DW, JT, NT, and PW packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . .	±0.5 V to 5.5	V
Current into any output in the low state, IO: SN54ABT827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 96 mA
SN74ABT827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 104°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 81°C/W
NT package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 120°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±65°C to 150°C

³ Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2.The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265