Texas Instruments SN74ABT823DW, SN74ABT823DWR, SN74ABT823NT, SN74ABT823DBLE, SN74ABT823DBR Datasheet

			SN54ABT823, SN74ABT823
	9-BIT BUS-INTERFACE FLIP-FLOPS
					WITH 3-STATE OUTPUTS
	SCBS158E ± JANUARY 1991 ± REVISED MAY 1997
D State-of-the-Art EPIC-ΙΙB BiCMOS Design	SN54ABT823 . . . JT OR W PACKAGE
Significantly Reduces Power Dissipation	SN74ABT823 . . . DB, DW, OR NT PACKAGE
D ESD Protection Exceeds 2000 V Per					(TOP VIEW)
MIL-STD-883, Method 3015; Exceeds 200 V							VCC
			OE		1	24
Using Machine Model (C = 200 pF, R = 0)			1D		2	23	1Q
D Latch-Up Performance Exceeds 500 mA Per			2D		3	22	2Q
JEDEC Standard JESD-17			3D		4	21	3Q
D Typical VOLP (Output Ground Bounce) < 1 V			4D		5	20	4Q
at VCC = 5 V, TA = 25°C			5D		6	19	5Q
			6D				6Q
					7	18
D High-Impedance State During Power Up
			7D				7Q
					8	17
and Power Down
			8D				8Q
					9	16
D High-Drive Outputs (±32-mA IOH, 64-mA IOL)
			9D				9Q
					10	15
D Buffered Control Inputs to Reduce
		CLR			11	14		CLKEN
dc Loading Effects	GND						CLK
					12	13

DPackage Options Include Plastic Small-Outline (DW) and Shrink

Small-Outline (DB) Packages, Ceramic Chip			SN54ABT823 . . . FK PACKAGE
Carriers (FK) and Flatpacks (W), and				(TOP VIEW)
							CC
Standard Plastic (NT) and Ceramic (JT)					OE	NC
			2D	1D			V 1Q	2Q
DIPs
description		3D	4	3	2	1	28 27 26		3Q
			5					25
These 9-bit flip-flops feature 3-state	outputs	4D	6					24	4Q
		5D	7					23	5Q
designed specifically for driving highly capacitive
		NC	8					22	NC
or relatively low-impedance loads. They are
		6D	9					21	6Q
particularly suitable for implementing wider buffer
		7D	10					20	7Q
registers, I/O ports, bidirectional bus drivers with
		8D	11					19	8Q
parity, and working registers.
			12 13 14 15 16 17 18
With the clock-enable (CLKEN) input low, the nine			9D	CLR	GND	NC	CLK CLKEN	9Q
low-to-high transitions of the clock. Taking CLKEN
D-type edge-triggered flip-flops enter data on the
high disables the clock buffer, thus latching the		NC ± No internal connection
outputs. Taking the clear (CLR) input low causes
the nine Q outputs to go low, independently of the
clock.

A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT823 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT823 is characterized for operation from ±40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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SN54ABT823, SN74ABT823

9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SCBS158E ± JANUARY 1991 ± REVISED MAY 1997

FUNCTION TABLE (each flip-flop)

				INPUTS					OUTPUT
							CLK	D	Q
	OE		CLR		CLKEN
	L		L		X		X	X	L
	L		H		L		↑	H	H
	L		H		L		↑	L	L
	L		H		H		X	X	Q0
	H		X		X		X	X	Z

logic symbol²

			1				EN
		OE
			11
							R
CLR
				14			G1
CLKEN
13
	CLK							1C2
2										23
		1D					2D				1Q
3										22
		2D									2Q
4										21
		3D									3Q
										20
5											4Q
		4D
6										19
		5D									5Q
										18
7											6Q
		6D
										17
8											7Q
		7D
										16
9											8Q
		8D
10										15
		9D									9Q

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, and W packages.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABT823, SN74ABT823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SCBS158E ± JANUARY 1991 ± REVISED MAY 1997

logic diagram (positive logic)

OE	1
CLR	11
CLKEN	14
CLK	13	R
		C1	23
				1Q
1D	2	1D

To Eight Other Channels

Pin numbers shown are for the DB, DW, JT, NT, and W packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . .	±0.5 V to 5.5	V
Current into any output in the low state, IO: SN54ABT823 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 96 mA
SN74ABT823 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 104°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 81°C/W
NT package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±65°C to 150°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. This is a stress ratingonly, and functional operation of the device at these or any other conditions beyond those indicated in the ªrecommended operating conditionsº section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2.The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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