Texas Instruments SN74ABT7819-20PN, SN74ABT7819-30PH, SN74ABT7819-30PN, SN74ABT7819-10PH, SN74ABT7819-10PN Datasheet

SN74ABT7819

512 ×18

×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G ± JULY 1992 ± REVISED JULY 1998

D Member of the Texas Instruments

D

Microprocessor Interface Control Logic

Widebus Family

D

Programmable Almost-Full/Almost-Empty

D Free-Running CLKA and CLKB Can Be

Flag

Asynchronous or Coincident

D Fast Access Times of 9 ns With a 50-pF

D Read and Write Operations Synchronized

Load and Simultaneous Switching Data

to Independent System Clocks

Outputs

D Two Separate 512 × 18 Clocked FIFOs

D

Data Rates up to 100 MHz

Buffering Data in Opposite Directions

D

Advanced BiCMOS Technology

D IRA and ORA Synchronized to CLKA

D Package Options Include 80-Pin Quad Flat

D IRB and ORB Synchronized to CLKB

(PH) and 80-Pin Thin Quad Flat (PN)

Packages

PH PACKAGE

(TOP VIEW)

CSA W/RA GND WENA

CLKA

RENA

ORA V V

ORB RENB

CLKB WENB GND W/RB

CSB

CC CC

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

1

64

RSTA

RSTB

PENA

2

63

PENB

AF/AEA

3

62

AF/AEB

HFA

4

61

HFB

IRA

5

60

IRB

GND

6

59

GND

A0

7

58

B0

A1

8

57

B1

VCC

9

56

VCC

A2

10

55

B2

A3

11

54

B3

GND

12

53

GND

A4

13

52

B4

A5

14

51

B5

GND

15

50

GND

A6

16

49

B6

A7

17

48

B7

GND

18

47

GND

A8

19

46

B8

A9

20

45

B9

VCC

21

44

VCC

A10

22

43

B10

A11

23

42

B11

GND

24

41

GND

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

A15

GND

A16 A17 B17

B16 GND

B15 B14 V B13 B12

A12 A13 V A14

CC

CC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1998, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN74ABT7819 512 ×18 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G ± JULY 1992 ± REVISED JULY 1998

PN PACKAGE (TOP VIEW)

PENA

RSTA

CSA W/RA

GND

WENA CLKA

RENA ORA

V

V

ORB

RENB

CLKB

WENB

GND

W/RB

CSB

RSTB

PENB

CC

CC

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

AF/AEA

1

60

AF/AEB

HFA

2

59

HFB

IRA

3

58

IRB

GND

4

57

GND

A0

5

56

B0

A1

6

55

B1

VCC

7

54

VCC

A2

8

53

B2

A3

9

52

B3

GND

10

51

GND

A4

11

50

B4

A5

12

49

B5

GND

13

48

GND

A6

14

47

B6

A7

15

46

B7

GND

16

45

GND

A8

17

44

B8

A9

18

43

B9

VCC

19

42

VCC

A10

20

41

B10

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

A11

GND A12 A13

V

A14 A15

GND A16

A17

B17

B16

GND

B15

B14

V

B13

B12

GND

B11

CC

CC

description

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ABT7819 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. Two independent 512 ×18 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions, a half-full flag, and a programmable almost-full/almost-empty flag.

The SN74ABT7819 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The state of the A0±A17 outputs is controlled by CSA and W/RA. When both CSA and W/RA are low, the outputs are active. The A0±A17 outputs are in the high-impedance state when either CSA or W/RA is high. Data is written to FIFOA±B from port A on the low-to-high transition of CLKA when CSA is low, W/RA is high, WENA is high, and the IRA flag is high. Data is read from FIFOB±A to the A0±A17 outputs on the low-to-high transition of CLKA when CSA is low, W/RA is low, RENA is high, and the ORA flag is high.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ABT7819 512 ×18 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G ± JULY 1992 ± REVISED JULY 1998

description (continued)

The state of the B0±B17 outputs is controlled by CSB and W/RB. When both CSB and W/RB are low, the outputs are active. The B0±B17 outputs are in the high-impedance state when either CSB or W/RB is high. Data is written to FIFOB±A from port B on the low-to-high transition of CLKB when CSB is low, W/RB is high, WENB is high, and the IRB flag is high. Data is read from FIFOA±B to the B0±B17 outputs on the low-to-high transition of CLKB when CSB is low, W/RB is low, RENB is high, and the ORB flag is high.

The setupand hold-time constraints for the chip selects (CSA, CSB) and write/read selects (W/RA, W/RB) enable write and read operations on memory and are not related to the high-impedance control of the data outputs. If a port read enable (RENA or RENB) and write enable (WENA or WENB) are set low during a clock cycle, the chip select and write/read select can switch at any time during the cycle to change the state of the data outputs.

The input-ready (IR) and output-ready (OR) flags of a FIFO are two-stage synchronized to the port clocks for use as reliable control signals. CLKA synchronizes the status of the input-ready flag of FIFOA±B (IRA) and the output-ready flag of FIFOB±A (ORA). CLKB synchronizes the status of the input-ready flag of FIFOB±A (IRB) and the output-ready flag of FIFOA±B (ORB). When the IR flag of a port is low, the FIFO receiving input from the port is full and writes are disabled to its array. When the OR flag of a port is low, the FIFO that outputs data to the port is empty and reads from its memory are disabled. The first word loaded to an empty memory is sent to the FIFO output register at the same time its OR flag is asserted (high). When the memory is read empty and the OR flag is forced low, the last valid data remains on the FIFO outputs until the OR flag is asserted (high) again. In this way, a high on the OR flag indicates new data is present on the FIFO outputs.

The SN74ABT7819 is characterized for operation from 0°C to 70°C.

Function Tables

PORT A

	SELECT INPUTS							A0±A17	PORT-A OPERATION
CLKA	CSA	W/RA			WENA	RENA
X	H	X			X	X		High Z	None
↑	L	H			H	X		High Z	Write A0±A17 to FIFOA±B
↑	L	L			X	H		Active	Read FIFOB±A to A0±A17
						PORT B
	SELECT INPUTS							B0±B17	PORT-B OPERATION
CLKB	CSB	W/RB			WENB	RENB
X	H	X			X	X		High Z	None
↑	L	H			H	X		High Z	Write B0±B17 to FIFOB±A
↑	L	L			X	H		Active	Read FIFOA±B to B0±B17

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

SN74ABT7819 512 ×18 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G ± JULY 1992 ± REVISED JULY 1998

logic symbol²

	76			F				69
	CLKA	CLOCK A		FIFO 512 × 18 × 2		CLOCK B		CLKB
	80	&		SN74ABT7819			&	65
	CSA		OE1			OE2		CSB
	79							66
	W/RA							W/RB
		&	WRITE			WRITE	&
	77		ENABLE			ENABLE		68
			FIFOA±B			FIFOB±A
	WENA							WENB
		&	READ			READ	&
	75		ENABLE			ENABLE		70
			FIFOB±A			FIFOA±B
	RENA							RENB
	1	RESET FIFO A±B			RESET FIFO B±A			64
	RSTA							RSTB
	2	PROGRAM ENABLE			PROGRAM ENABLE			63
	PENA							PENB
	5	FIFO A±B				FIFO B±A		60
		INPUT-READY				INPUT-READY
	IRA							IRB
	74	PORT A				PORT B		71
		OUTPUT-READY				OUTPUT-READY
	ORA							ORB
	4	PORT A				PORT B		61
		HALF-FULL				HALF-FULL
	HFA							HFB
	3	FIFOA±B				FIFOB±A		62
		ALMOST-FULL/EMPTY			ALMOST-FULL/EMPTY
	AF/AEA							AF/AEB
		FIFOA±B				FIFOB±A
	7	0					0	58
	A0							B0
	8							57
	A1							B1
	10							55
	A2							B2
	11							54
	A3							B3
	13							52
	A4							B4
	14							51
	A5							B5
	16							49
	A6							B6
	17							48
	A7							B7
	19		1			2		46
	A8							B8
	20		Data			Data		45
	A9							B9
	22							43
	A10							B10
	23							42
	A11							B11
	25							40
	A12							B12
	26							39
	A13							B13
	28							37
	A14							B14
	29							36
	A15							B15
	31							34
	A16							B16
	32	17					17	33
	A17							B17

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the PH package.

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ABT7819 512 ×18 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G ± JULY 1992 ± REVISED JULY 1998

functional block diagram

PENA
RENA
WENA	Port-A
CSA	Control
	Logic
W/RA
			Read
CLKA
			Pointer
RSTA
		18	512 × 18
			Dual-Port SRAM	Register
		Register	FIFOB±A
	18				18
			Write
			Pointer
		Flag			IRB
ORA		Logic			AF/AEB
		FIFOB±A	8		HFB
A0±A17					B0±B17
	8
IRA			Flag
AF/AEA
			Logic		ORB
HFA
			FIFOA±B
		Write
		Pointer
	18	512 × 18
		Dual-Port SRAM	Register
	Register
		FIFOA±B
		Read
		Pointer			RSTB
					CLKB
				Port-B	CSB
					W/RB
				Control
				Logic	WENB
					RENB
					PENB

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

SN74ABT7819 512 ×18 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G ± JULY 1992 ± REVISED JULY 1998

enable logic diagram (positive logic)

CSA
W/RA	WEN FIFOA±B
WENA
	A0±A17 (output enable)
RENA	REN FIFOB±A

CSB

WEN FIFOB±A W/RB

WENB

B0±B17 (output enable)

REN FIFOA±B

RENB

Terminal Functions

TERMINAL²

I/O

DESCRIPTION

NAME

NO.

7±8, 10±11,

13±14, 16±17,

A0±A17

19±20, 22±23,

I/O

Port-A data. The 18-bit bidirectional data port for side A.

25±26, 28±29,

31±32

FIFOA±B almost-full/almost-empty flag. Depth offsets can be programmed for AF/AEA or the default

AF/AEA

3

O

value of 128 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEA is

high when X or fewer words or (512 ± Y) or more words are stored in FIFOA±B. AF/AEA is forced high

when FIFOA±B is reset.

FIFOB±A almost-full/almost-empty flag. Depth offsets can be programmed for AF/AEB or the default

AF/AEB

62

O

value of 128 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEB is

high when X or fewer words or (512 ± Y) or more words are stored in FIFOB±A. AF/AEB is forced high

when FIFOB±A is reset.

58±57, 55±54,

52±51, 49±48,

B0±B17

46±45, 43±42,

I/O

Port-B data. The 18-bit bidirectional data port for side B.

40±39, 37±36,

34±33

CLKA

76

I

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A to its

low-to-high transition and can be asynchronous or coincident to CLKB.

CLKB

69

I

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B to its

low-to-high transition and can be asynchronous or coincident to CLKA.

Port-A chip select.

must be low to enable a low-to-high transition of CLKA to either write data from

CSA

CSA

80

I

A0±A17 to FIFOA±B or read data from FIFOB±A to A0±A17. The A0±A17 outputs are in the

high-impedance state when CSA is high.

Port-B chip select.

must be low to enable a low-to-high transition of CLKB to either write data from

CSB

CSB

65

I

B0±B17 to FIFOB±A or read data from FIFOA±B to B0±B17. The B0±B17 outputs are in the

high-impedance state when CSB is high.

² Terminals listed are for the PH package.

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265