Texas Instruments SN74ABT646ADBLE, SN74ABT646ADBR, SN74ABT646ADGVR, SN74ABT646ADW, SN74ABT646ADWR Datasheet

	SN54ABT646A, SN74ABT646A
	OCTAL BUS TRANSCEIVERS AND REGISTERS
				WITH 3-STATE OUPUTS
	SCBS069G ± JULY 1991 ± REVISED MAY 1997
D State-of-the-Art EPIC-ΙΙB BiCMOS Design	SN54ABT646A . . . JT OR W PACKAGE
Significantly Reduces Power Dissipation	SN74ABT646A . . . DB, DW, NT, OR PW PACKAGE
D ESD Protection Exceeds 2000 V Per		(TOP VIEW)
MIL-STD-883, Method 3015; Exceeds 200 V	CLKAB		1	24			VCC
Using Machine Model (C = 200 pF, R = 0)
	SAB		2	23			CLKBA
D Latch-Up Performance Exceeds 500 mA Per	DIR		3	22			SBA
JEDEC Standard JESD-17	A1
			4	21			OE
D Typical VOLP (Output Ground Bounce)	A2		5	20			B1
	A3		6	19			B2
< 1 V at VCC = 5 V, TA = 25°C
	A4		7	18			B3
D High-Drive Outputs (±32-mA IOH, 64-mA IOL)
	A5		8	17			B4
D Package Options Include Plastic	A6		9	16			B5
Small-Outline (DW), Shrink Small-Outline	A7		10	15			B6
(DB), and Thin Shrink Small-Outline (PW)
	A8		11	14			B7
Packages, Ceramic Chip Carriers (FK),
	GND		12	13			B8
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs	SN54ABT646A . . . FK PACKAGE

description

These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 'ABT646A.

Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either register or in both.

(TOP VIEW)

	DIR	SAB	CLKAB	NC	CC	CLKBA	SBA
					V
A1	4	3	2	1	28 27 26			OE
	5						25
A2	6						24	B1
A3	7						23	B2
NC	8						22	NC
A4	9						21	B3
A5	10						20	B4
A6	11						19	B5
	12 13 14 15 16 17						18
	A7	A8	GND	NC	B8	B7	B6

NC ± No internal connection

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high), A data can be stored in one register and/or B data can be stored in the other register.

When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT646A is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT646A is characterized for operation from ±40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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SN54ABT646A, SN74ABT646A

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUPUTS

SCBS069G ± JULY 1991 ± REVISED MAY 1997

BUS A

BUS B

BUS A

BUS B

21

3

1

23

2

22

21

3

1

23

2

22

OE

DIR

CLKAB CLKBA

SAB

SBA

OE

DIR

CLKAB

CLKBA

SAB

SBA

L

L

X

X

X

L

L

H

X

X

L

X

REAL-TIME TRANSFER

REAL-TIME TRANSFER

BUS B TO BUS A

BUS A TO BUS B

BUS A

BUS B

BUS A

BUS B

21	3	1	23	2	22	21	3	1	23	2	22
OE	DIR	CLKAB CLKBA		SAB	SBA	OE	DIR	CLKAB	CLKBA	SAB	SBA
X	X	↑	X	X	X	L	L	X	L	X	H
X	X	X	↑	X	X	L	H	L	X	H	X
H	X	↑	↑	X	X
		STORAGE FROM					TRANSFER STORED DATA
		A, B, OR A AND B						TO A AND/OR B

Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

Figure 1. Bus-Management Functions

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABT646A, SN74ABT646A

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUPUTS

									SCBS069G ± JULY 1991 ± REVISED MAY 1997
						FUNCTION TABLE
			INPUTS				DATA I/Os			OPERATION OR FUNCTION
OE		DIR	CLKAB	CLKBA	SAB	SBA	A1±A8	B1±B8
	X	X	↑	X	X	X	Input	Unspecified²		Store A, B unspecified²
	X	X	X	↑	X	X	Unspecified²	Input		Store B, A unspecified²
	H	X	↑	↑	X	X	Input	Input		Store A and B data
	H	X	H or L	H or L	X	X	Input disabled	Input disabled		Isolation, hold storage
	L	L	X	X	X	L	Output	Input		Real-time B data to A bus
	L	L	X	H or L	X	H	Output	Input		Stored B data to A bus
	L	H	X	X	L	X	Input	Output		Real-time A data to B bus
	L	H	H or L	X	H	X	Input	Output		Stored A data to B bus

²The data-output functions may be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

logic symbol³

		21					G3
	OE
		3
DIR							3 EN1 [BA]
		23					3 EN2 [AB]
CLKBA								C4
		22
SBA							G5
		1
CLKAB								C6
		2
SAB							G7

					20
4	≥	1	5	4D	B1
A1	1		5	1
	6D		7	≥ 1
	1		7	2
5					19
A2
					B2
6					18
A3					B3
7					17
A4					B4
8					16
A5					B5
9					15
A6					B6
10					14
A7					B7
11					13
A8					B8

³ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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