Texas Instruments SN74AC573DBLE, SN74AC573DBR, SN74AC573DW, SN74AC573DWR, SN74AC573N Datasheet

				SN54AC573, SN74AC573
		OCTAL D-TYPE TRANSPARENT LATCHES
				WITH 3-STATE OUTPUTS
		SCAS542B - OCTOBER 1995 ± REVISED NOVEMBER 1996
D 3-State Outputs Drive Bus Lines Directly		SN54AC573 . . . J OR W PACKAGE
D	EPIC (Enhanced-Performance Implanted	SN74AC573 . . . DB, DW, N, OR PW PACKAGE
				(TOP VIEW)
	CMOS) 1- m Process
D Package Options Include Plastic			OE	1		20	VCC
	Small-Outline (DW) Shrink Small-Outline		1D	2		19	1Q
	(DB), and Thin Shrink Small-Outline (PW)		2D	3		18	2Q
	Packages, Ceramic Chip Carriers (FK) and		3D	4		17	3Q
	Flatpacks (W), and Standard Plastic (N) and		4D	5		16	4Q
	Ceramic (J) DIPs		5D	6		15	5Q
description			6D	7		14	6Q
			7D	8		13	7Q
	These 8-bit latches feature 3-state outputs		8D	9		12	8Q
		GND		10		11	LE
	designed specifically for driving highly capacitive
	or relatively low-impedance loads. The devices
	are particularly suitable for implementing buffer	SN54AC573 . . . FK PACKAGE
	registers, I/O ports, bidirectional bus drivers, and
				(TOP VIEW)
	working registers.					CC
	The eight latches are D-type transparent latches.		2D	1D	OE		1Q
						V
	When the latch-enable (LE) input is high, the Q		3	2	1	20 19
	outputs follow the data (D) inputs. When LE is	3D						2Q
			4				18
	taken low, the Q outputs are latched at the logic
		4D	5				17	3Q
	levels set up at the D Inputs.
		5D	6				16	4Q
	A buffered output-enable (OE) input can be used	6D	7				15	5Q
	to place the eight outputs in either a normal logic	7D	8				14	6Q
	state (high or low logic levels) or the high-imped-		9	10 11 12 13
	ance state. In the high-impedance state, the		8D	GND	LE	8Q	7Q
	outputs neither load nor drive the bus lines
	significantly. The high-impedance state and
	increased drive provide the capability to drive bus
	lines in a bus-organized system without need for
	interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54AC573 is characterized for operation over the full military temperature range of ±55_C to 125_C. The SN74AC573 is characterized for operation from ±40_C to 85_C.

FUNCTION TABLE (each latch)

		INPUTS		OUTPUT
		LE	D	Q
	OE
	L	H	H	H
	L	H	L	L
	L	L	X	Q0
	H	X	X	Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1996, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN54AC573, SN74AC573

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS542B - OCTOBER 1995 ± REVISED NOVEMBER 1996

logic symbol²

logic diagram (positive logic)

		1		EN
OE
11
	LE			C1
2							19
	1D			1D				1Q
3							18
	2D							2Q
4							17
	3D							3Q
5							16
	4D							4Q
							15
6								5Q
	5D
							14
7								6Q
	6D
							13
8								7Q
	7D
							12
9								8Q
	8D

	OE	1
	LE	11
		C1	19	1Q
	1D	2
		1D
		To Seven Other Channels

²This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±0.5 V to + 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±50 mA
Continuous current through, VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . ±200 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . .	. . . . . . . . . . . . . 0.6 W
DW package . . . . .	. . . . . . . . . . . . . 1.6 W
N package . . . . . . .	. . . . . . . . . . . . . 1.3 W
PW package . . . . .	. . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . ±65°C to 150°C

³ Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2.The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265