Texas Instruments SN74ACT3651-15PCB, SN74ACT3651-15PQ, SN74ACT3651-20PCB, SN74ACT3651-20PQ, SN74ACT3651-30PCB Datasheet

						SN74ACT3651
				2048 ×36
				CLOCKED FIRST-IN, FIRST-OUT MEMORY
				SCAS439D ± JUNE 1994 ± REVISED FEBRUARY 1999
D Free-Running CLKA and CLKB Can Be				D Output-Ready and		Flags Synchronized
					AE
	Asynchronous or Coincident			by CLKB
D Clocked FIFO Buffering Data From Port A				D Low-Power 0.8-mm Advanced CMOS
	to Port B			Technology
D	Synchronous Read-Retransmit Capability			D Supports Clock Frequencies up to 67 MHz
D Mailbox Register in Each Direction				D Fast Access Times of 11 ns
D	Programmable Almost-Full and			D Pin-to-Pin Compatible With SN74ACT3631
	Almost-Empty Flags			and SN74ACT3641
D Microprocessor Interface Control Logic				D Package Options Include 120-Pin Thin
D Input-Ready and			Flags Synchronized by	Quad Flat (PCB) and 132-Pin Plastic Quad
		AF
	CLKA			Flat (PQ) Packages

description

The SN74ACT3651 is a high-speed, low-power, CMOS clocked FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 11 ns. The 2048 × 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag that signals when new mail has been stored. Two or more devices are used in parallel to create wider data paths. Expansion is also possible in word depth.

The SN74ACT3651 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control.

The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to CLKA. The output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offset values for AF and AE are programmed from port A or through a serial input.

The SN74ACT3651 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the following application reports:

•FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering

(literature number SCAA009)

•FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number SCAA007)

•Metastability Performance of Clocked FIFOs (literature number SCZA004)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1999, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN74ACT3651 2048 ×36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS439D ± JUNE 1994 ± REVISED FEBRUARY 1999

PCB PACKAGE (TOP VIEW)

		GND CLKA				ENA		W/RA		CSA			IR		OR			V			AF		AE V					MBF2			MBA		RST GND					FS0/SD			FS1/SEN			RTM RFM				V			NC		MBB			GND				MBF1	GND			CSB W/RB				ENB			CLKB			V
																			CC						CC																								CC																										CC
A35		120		119		118		117		116			115		114			113			112		111	110			109			108			107	106			105			104			103		102			101			100		99			98			97		96			95		94		93			92			91
		1																																																																								90
A34		2																																																																								89
A33		3																																																																								88
A32		4																																																																								87
VCC		5																																																																								86
A31		6																																																																								85
A30		7																																																																								84
GND		8																																																																								83
A29		9																																																																								82
A28		10																																																																								81
A27		11																																																																								80
A26		12																																																																								79
A25		13																																																																								78
A24		14																																																																								77
A23		15																																																																								76
GND		16																																																																								75
A22		17																																																																								74
VCC		18																																																																								73
A21		19																																																																								72
A20		20																																																																								71
A19		21																																																																								70
A18		22																																																																								69
GND		23																																																																								68
A17		24																																																																								67
A16		25																																																																								66
A15		26																																																																								65
A14		27																																																																								64
A13		28																																																																								63
VCC		29																																																																								62
A12		30																																																																								61
		31		32		33		34		35			36		37			38			39		40	41			42			43			44	45			46			47			48		49			50			51		52			53			54		55			56		57		58			59			60
			GND A11 A10					A9		A8			A7			A6			GND		A5		A4 A3				V			A2			A1	A0			GND			B0			B1			B2			B3		B4		B5			GND								B7		B8 B9									B11
																																																												B6 V												B10
																												CC																																		CC

NC ± No internal connection

B35

B34

B33

B32 GND B31 B30 B29 B28 B27 B26

VCC

B25

B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16

VCC

B15

B14

B13

B12 GND

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ACT3651 2048 ×36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS439D ± JUNE 1994 ± REVISED FEBRUARY 1999

PQ PACKAGE² (TOP VIEW)

												CLKB		ENB W/RB												MBF1																				FS1/SEN			FS0/SD													MBF2																								W/RA					CLKA
				NC			NC		V											CSB			GND					GND			MBB			NC			V			RFM		RTM										GND			RST				MBA					V			AE				AF			V				OR		IR				CSA				ENA						GND			NC
										CC																												CC																											CC										CC
	17 16 15 14 13 12 11 10																									9		8			7			6			5			4		3			2				1 132									130						128						126							124						122					120						118
NC			18																																																	131							129								127							125						123						121					119						117
																																																																																																	116
B35			19																																																																																														115
B34			20																																																																																														114
B33			21																																																																																														113
B32			22																																																																																														112
GND			23																																																																																														111
B31			24																																																																																														110
B30			25																																																																																														109
B29			26																																																																																														108
B28			27																																																																																														107
B27			28																																																																																														106
B26			29																																																																																														105
VCC			30																																																																																														104
B25			31																																																																																														103
B24			32																																																																																														102
GND			33																																																																																														101
B23			34																																																																																														100
B22			35																																																																																														99
B21			36																																																																																														98
B20			37																																																																																														97
B19			38																																																																																														96
B18			39																																																																																														95
GND			40																																																																																														94
B17			41																																																																																														93
B16			42																																																																																														92
VCC			43																																																																																														91
B15			44																																																																																														90
B14			45																																																																																														89
B13			46																																																																																														88
B12			47																																																																																														87
GND			48																																																																																														86
NC			49																																																																																														85
NC			50																																																																																														84
			51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
				NC			B11		B10			B9		B8 B7						V			B6			GND		B5			B4			B3			B2			B1		B0				GND			A0			A1			A2				V			A3			A4		A5				GND			A6			A7				A8			A9		A10		A11			GND			NC			NC
																					CC																																							CC

NC ± No internal connection

² Uses Yamaichi socket IC51-1324-828

NC

NC

A35

A34

A33

A32

VCC

A31

A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22

VCC

A21

A20

A19

A18 GND A17 A16 A15 A14 A13

VCC

A12

NC

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

SN74ACT3651 2048 ×36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS439D ± JUNE 1994 ± REVISED FEBRUARY 1999

functional block diagram

			Mail1
CLKA			Register
CSA	Port-A
W/RA	Control
ENA	Logic	Register
MBA			2048 × 36
RST		Input	SRAM
	Reset
	Logic
		36
			Write	Read
			Pointer	Pointer
A0 ± A35
IR			Status-Flag
AF			Logic
FS0/SD			Flag-Offset
FS1/SEN			Register
		10
			Mail2
			Register
MBF2

Output Register
Synch	Retransmit	Logic

MBF1

RTM

RFM

B0 ± B35

OR

AE

CLKB

Port-B CSB

Control W/RB

Logic

ENB

MBB

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ACT3651

2048 ×36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS439D ± JUNE 1994 ± REVISED FEBRUARY 1999

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

A0±A35

I/O

Port-A data. The 36-bit bidirectional data port for side A.

Almost-empty flag. Programmable flag synchronized to CLKB.

AE

is low when the number of words in the FIFO is less

AE

O

than or equal to the value in the almost-empty offset register (X).

Almost-full flag. Programmable flag synchronized to CLKA.

is low when the number of empty locations in the FIFO

AF

AF

O

is less than or equal to the value in the almost-full offset register (Y).

B0±B35

I/O

Port-B data. The 36-bit bidirectional data port for side B.

CLKA

I

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous

or coincident to CLKB. IR and AF are synchronous to the low-to-high transition of CLKA.

CLKB

I

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous

or coincident to CLKA. OR and AE are synchronous to the low-to-high transition of CLKB.

I

Port-A chip select.

CSA

must be low to enable a low-to-high transition of CLKA to read or write data on port A. The

CSA

A0 ± A35 outputs are in the high-impedance state when CSA is high.

I

Port-B chip select.

CSB

must be low to enable a low-to-high transition of CLKB to read or write data on port B. The

CSB

B0 ± B35 outputs are in the high-impedance state when CSB is high.

ENA

I

Port-A master enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.

ENB

I

Port-B master enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.

Flag-offset select 1/serial enable, flag-offset select 0/serial data. FS1/

SEN

and FS0/SD are dual-purpose inputs used

for flag-offset-register programming. During a device reset, FS1/SEN and FS0/SD select the flag-offset programming

method. Three offset-register programming methods are available: automatically load one of two preset values,

parallel load from port A, and serial load.

FS1/SEN,

I

FS0/SD

When serial load is selected for flag-offset-register programming, FS1/SEN is used as an enable synchronous to the

low-to-high transition of CLKA. When FS1/SEN is low, a rising edge on CLKA loads the bit present on FS0/SD into

the X-and Y-offset registers. The number of bit writes required to program the offset registers is 22. The first bit write

stores the Y-register MSB and the last bit write stores the X-register LSB.

Input-ready flag. IR is synchronized to the low-to-high transition of CLKA. When IR is low, the FIFO is full and writes

IR

O

to its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the

point of the retransmit data and prevents further writes. IR is set low during reset and is set high after reset.

MBA

I

Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.

Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the

MBB

I

B0 ± B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects

FIFO data for output.

Mail1 register flag.

MBF1

is set low by the low-to-high transition of CLKA that writes data to the mail1 register.

MBF1

MBF1

O

is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high by

a reset.

Mail2 register flag.

is set low by the low-to-high transition of CLKB that writes data to the mail2 register.

MBF2

MBF2

MBF2

O

is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high by

a reset.

Output-ready flag. OR is synchronized to the low-to-high transition of CLKB. When OR is low, the FIFO is empty and

OR

O

reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during

the reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory.

RFM

I

Read from mark. When the FIFO is in retransmit mode, a high on RFM enables a low-to-high transition of CLKB to

reset the read pointer to the beginning retransmit location and output the first selected retransmit data.

I

Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur

RST

while RST is low. The low-to-high transition of RST latches the status of FS0 and FS1 for AF and AE offset selection.

Retransmit mode. When RTM is high and valid data is present in the FIFO output register (OR is high), a low-to-high

RTM

I

transition of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected

word remains the initial retransmit point until a low-to-high transition of CLKB occurs while RTM is low, taking the FIFO

out of retransmit mode.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

SN74ACT3651 2048 ×36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS439D ± JUNE 1994 ± REVISED FEBRUARY 1999

							Terminal Functions (Continued)
	TERMINAL					I/O					DESCRIPTION
	NAME
						I	Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for
	W/RA
							a low-to-high transition of CLKA. The A0 ± A35 outputs are in the high-impedance state when W/RA is high.
							Port-B write/read select. A low on
						I		W/RB selects a write operation and a high selects a read operation on port B for
	W/RB
							a low-to-high transition of CLKB. The B0 ± B35 outputs are in the high-impedance state when W/RB is low.

detailed description

reset

The SN74ACT3651 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A reset initializes the memory-read and-write pointers and forces the IR flag low, the OR flag high, the AE flag low, and the AF flag high. Resetting the device also forces the mailbox flags (MBF1, MBF2) high. After a FIFO is reset, IR is set high after at least two clock cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory.

almost-empty flag and almost-full flag offset programming

Two registers in the SN74ACT3651 are used to hold the offset values for the AE and AF flags. The AE flag offset register is labeled X, and the AF flag offset register is labeled Y. The offset registers can be loaded with a value in three ways: one of two preset values is loaded into the offset registers, parallel load from port A, or serial load. The offset-register-programming mode is chosen by the flag select (FS1, FS0) inputs during a low-to-high transition on RST (see Table 1).

Table 1. Flag Programming

FS1	FS0	RST	X AND Y REGISTERS²
H	H	↑	Serial load
H	L	↑	64
L	H	↑	8
L	L	↑	Parallel load from port A

²X register holds the offset for AE; Y register holds the offset for AF.

preset values

If a preset value of 8 or 64 is chosen by FS1 and FS0 at the time of an RST low-to-high transition according to Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on CLKA.

parallel load from port A

To program the X and Y registers from port A, the device is reset with FS0 and FS1 low during the low-to-high transition of RST. After this reset is complete, the IR flag is set high after two low-to-high transitions on CLKA. The first two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X. Each offset register of the SN74ACT3651 uses port-A inputs (A10±A0). The highest number input is used as the most-significant bit of the binary number in each case. Each register value can be programmed from 1 to 2044. After both offset registers are programmed from port A, subsequent FIFO writes store data in the SRAM.

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ACT3651 2048 ×36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS439D ± JUNE 1994 ± REVISED FEBRUARY 1999

serial load

To program the X and Y registers serially, the device is reset with FS0/SD and FS1/SEN high during the low-to-high transition of RST. After this reset is complete, the X-and Y-register values are loaded bitwise through FS0/SD on each low-to-high transition of CLKA that FS1/SEN is low. Twenty-two bit writes are needed to complete the programming. The first bit write stores the most-significant bit of the Y register and the last bit write stores the least-significant bit of the X register. Each register value can be programmed from 1 to 2044.

When the option is chosen to program the offset registers serially, the IR flag remains low until all register bits are written. The IR flag is set high by the low-to-high transition of CLKA after the last bit is loaded, to allow normal FIFO operation.

FIFO write/read operation

The state of the port-A data (A0±A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0±A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0±A35 outputs are active when both CSA and W/RA are low.

Data is loaded into the FIFO from the A0±A35 inputs on a low-to-high transition of CLKA when CSA and the port-A mailbox select (MBA) are low, W/RA, the port-A enable (ENA), and the IR flag are high (see Table 2). Writes to the FIFO are independent of any concurrent FIFO reads.

Table 2. Port-A Enable Function Table

CSA	W/RA			ENA	MBA	CLKA	A0 ± A35 OUTPUTS	PORT FUNCTION
H	X			X	X	X	In high-impedance state	None
L	H			L	X	X	In high-impedance state	None
L	H			H	L	↑	In high-impedance state	FIFO write
L	H			H	H	↑	In high-impedance state	Mail1 write
L	L			L	L	X	Active, mail2 register	None
L	L			H	L	↑	Active, mail2 register	None
L	L			L	H	X	Active, mail2 register	None
						↑
L	L			H	H		Active, mail2 register	Mail2 read (set	MBF2	high)

The port-B control signals are identical to those of port A, with the exception that the port-B write/read select (W/RB) is the inverse of the W/RA. The state of the port-B data (B0±B35) outputs is controlled by the port-B chip select (CSB) and W/RB. The B0±B35 outputs are in the high-impedance state when either CSB is high or W/RB is low. The B0±B35 outputs are active when CSB is low and W/RB is high.

Data is read from the FIFO to its output register on a low-to-high transition of CLKB when CSB and MBB are low, W/RB, ENB, and the OR flag are high (see Table 3). Reads from the FIFO are independent of any concurrent FIFO writes.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

7

SN74ACT3651

2048

×36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS439D ± JUNE 1994 ± REVISED FEBRUARY 1999

Table 3. Port-B Enable Function Table

CSB

W/RB

ENB

MBB

CLKB

B0 ± B35 OUTPUTS

PORT FUNCTION

H

X

X

X

X

In high-impedance state

None

L

L

L

X

X

In high-impedance state

None

L

L

H

L

↑

In high-impedance state

None

L

L

H

H

↑

In high-impedance state

Mail2 write

L

H

L

L

X

Active, FIFO output register

None

L

H

H

L

↑

Active, FIFO output register

FIFO read

L

H

L

H

X

Active, mail1 register

None

↑

L

H

H

H

Active, mail1 register

Mail1 read (set

MBF1

high)

The setupand hold-time constraints to the port clocks for the port-chip selects and write/read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select can change states during the setupand hold-time window of the cycle.

When OR is low, the next data word is sent to the FIFO output register automatically by the CLKB low-to-high transition that sets OR high. When OR is high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by CSB, W/RB, ENB, and MBB.

synchronized FIFO flags

Each FIFO flag is synchronized to its port clock through at least two flip-flop stages. This is done to improve the flag's reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate asynchronously with one another. OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA. Table 4 shows the relationship of each flag to the number of words stored in memory.

Table 4. FIFO Flag Operation

	NUMBER OF WORDS IN	SYNCHRONIZED		SYNCHRONIZED
		TO CLKB		TO CLKA
	FIFO²³
		OR	AE	AF	IR
	0	L	L	H	H
	1 to X	H	L	H	H
	(X + 1) to [2048 ± (Y + 1)]	H	H	H	H
	(2048 ± Y) to 2047	H	H	L	H
	2048	H	H	L	L

² X is the almost-empty offset for AE. Y is the almost-full offset for AF.

³When a word is present in the FIFO output register, its previous memory location is free.

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265