Texas Instruments SN74ABT853DBLE, SN74ABT853DBR, SN74ABT853DW, SN74ABT853DWR, SN74ABT853NT Datasheet
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SN54ABT853, SN74ABT853 |
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8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS |
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SCBS198F ± FEBRUARY 1991 ± REVISED OCTOBER 1997 |
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D State-of-the-Art EPIC-ΙΙB BiCMOS Design |
SN54ABT853 . . . JT OR W PACKAGE |
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Significantly Reduces Power Dissipation |
SN74ABT853 . . . DB, DW, NT, OR PW PACKAGE |
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D ESD Protection Exceeds 2000 V Per |
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(TOP VIEW) |
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MIL-STD-883, Method 3015; Exceeds 200 V |
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VCC |
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OEA |
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1 |
24 |
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Using Machine Model (C = 200 pF, R = 0) |
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A1 |
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2 |
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B1 |
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D Latch-Up Performance Exceeds 500 mA Per |
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A2 |
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3 |
22 |
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B2 |
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JESD 17 |
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A3 |
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4 |
21 |
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B3 |
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D Typical VOLP (Output Ground Bounce) |
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A4 |
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5 |
20 |
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B4 |
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< 1 V at VCC = 5 V, TA = 25°C |
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A5 |
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6 |
19 |
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B5 |
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A6 |
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B6 |
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7 |
18 |
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D High-Drive Outputs (±32-mA IOH, 64-mA IOL) |
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A7 |
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B7 |
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8 |
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D High-Impedance State During Power Up |
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A8 |
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B8 |
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9 |
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and Power Down |
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ERR |
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10 |
15 |
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PARITY |
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D Parity-Error Flag With Parity |
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CLR |
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11 |
14 |
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OEB |
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Generator/Checker |
GND |
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LE |
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12 |
13 |
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DLatch for Storage of Parity-Error Flag
D Package Options Include Plastic |
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SN54ABT853 . . . FK PACKAGE |
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Small-Outline (DW), Shrink Small-Outline |
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(TOP VIEW) |
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(DB), and Thin Shrink Small-Outline (PW) |
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A2 |
A1 |
OEA |
NC |
V B1 |
B2 |
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Packages, Ceramic Chip Carriers (FK), |
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CC |
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Ceramic Flat (W) Package, and Plastic (NT) |
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and Ceramic (JT) DIPs |
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4 |
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2 |
1 |
28 27 26 |
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description |
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A3 |
5 |
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25 |
B3 |
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A4 |
6 |
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24 |
B4 |
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The 'ABT853 8-bit to 9-bit parity transceivers are |
A5 |
7 |
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23 |
B5 |
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NC |
8 |
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22 |
NC |
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designed for communication between data buses. |
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A6 |
9 |
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21 |
B6 |
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When data is transmitted from the A bus to the |
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A7 |
10 |
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20 |
B7 |
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B bus, a parity bit is generated. When data is |
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A8 |
11 |
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19 |
B8 |
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transmitted from the B bus to the A bus with its |
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12 13 14 15 16 17 18 |
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corresponding |
parity |
bit, |
the |
open-collector |
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ERR |
CLR |
GND |
NC |
LE OEB |
PARITY |
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parity-error (ERR) output indicates whether or not |
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an error in the B data has occurred. The |
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output-enable (OEA and OEB) inputs can be used |
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to disable the device so that |
the buses are |
NC ± No internal connection |
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effectively isolated. The 'ABT853 transceivers |
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provide true data at their outputs. |
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A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F ± FEBRUARY 1991 ± REVISED OCTOBER 1997
description (continued)
The SN54ABT853 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT853 is characterized for operation from ±40°C to 85°C.
FUNCTION TABLE
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INPUTS |
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OUTPUTS AND I/Os |
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Ai |
Bi² |
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FUNCTION |
OEB |
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OEA |
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CLR |
LE |
A |
B |
PARITY |
ERR³ |
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Σ OF H |
Σ OF H |
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L |
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H |
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X |
X |
Odd |
NA |
NA |
A |
L |
NA |
A data to B bus and |
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Even |
H |
generate parity |
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H |
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L |
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X |
L |
NA |
Odd |
B |
NA |
NA |
H |
B data to A bus and |
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Even |
L |
check parity |
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H |
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L |
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H |
H |
NA |
X |
X |
NA |
NA |
NC |
Store error flag |
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X |
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X |
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L |
H |
X |
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X |
NA |
NA |
H |
Clear error flag register |
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H |
H |
X |
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NC |
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H |
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H |
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L |
H |
X |
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Z |
Z |
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H |
Isolation§ |
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X |
L |
L Odd |
H |
(parity check) |
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X |
L |
H Even |
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L |
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L |
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L |
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X |
X |
Odd |
NA |
NA |
A |
H |
NA |
A data to B bus and |
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Even |
L |
generate inverted parity |
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NA = not applicable, NC = no change, X = don't care
² Summation of high-level inputs includes PARITY along with Bi inputs. ³ Output states shown assume ERR was previously high.
§ In this mode, ERR (when clocked) shows inverted parity of the A bus.
logic symbol¶
13 |
LE |
Φ |
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LE |
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11 |
CLR |
ERR |
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CLR |
ERR |
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1 |
OEA |
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OEA |
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14 |
OEB |
PARITY |
15 |
OEB |
PARITY |
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2 |
1 |
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23 |
A1 |
B1 |
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3 |
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22 |
A2 |
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B2 |
4 |
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21 |
A3 |
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B3 |
5 |
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20 |
A4 |
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B4 |
6 |
A Bus |
B Bus |
19 |
A5 |
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B5 |
7 |
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18 |
A6 |
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B6 |
8 |
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17 |
A7 |
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B7 |
9 |
8 |
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16 |
A8 |
B8 |
¶ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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SN54ABT853, SN74ABT853 |
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8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS |
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SCBS198F ± FEBRUARY 1991 ± REVISED OCTOBER 1997 |
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logic diagram (positive logic) |
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A1± A8 |
2±9 |
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8x |
23±16 |
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8 |
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B1±B8 |
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EN |
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8x |
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8 |
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EN |
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OEB |
14 |
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1 |
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15 |
OEA |
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8 |
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PARITY |
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8 |
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1 |
MUX |
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1 |
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2k |
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9 |
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1 |
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P |
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1 |
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G1 |
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13 |
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10 |
LE |
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ERR |
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CLR |
11 |
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Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
ERROR-FLAG FUNCTION TABLE
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INPUTS |
INTERNAL |
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OUTPUT |
OUTPUT |
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TO DEVICE |
PRESTATE |
FUNCTION |
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ERR |
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LE |
POINT P |
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N±1² |
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CLR |
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ERR |
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L |
L |
L |
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X |
L |
Pass |
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H |
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H |
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L |
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X |
L |
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H |
L |
X |
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L |
L |
Sample |
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H |
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H |
H |
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L |
H |
X |
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X |
H |
Clear |
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H |
H |
X |
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L |
L |
Store |
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H |
H |
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² The state of ERR before changes at CLR, LE, or point P
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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