Texas Instruments SN74ABT3611-30PCB, SN74ABT3611-30PQ, SN74ABT3611-15PCB, SN74ABT3611-15PQ, SN74ABT3611-20PCB Datasheet

SN74ABT3611 64 ×36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCBS127E ± JULY 1992 ± REVISED APRIL 1998

DFree-Running CLKA and CLKB Can Be Asynchronous or Coincident

D64 × 36 Clocked FIFO Buffering Data From

Port A to Port B

DMailbox-Bypass Register In Each Direction

DProgrammable Almost-Full and Almost-Empty Flags

DMicroprocessor Interface Control Logic

DFull Flag and Almost-Full Flag Synchronized by CLKA

description

DEmpty Flag and Almost-Empty Flag Synchronized by CLKB

DPassive Parity Checking on Each Port

DParity Generation Can Be Selected for Each Port

DLow-Power Advanced BiCMOS Technology

DSupports Clock Frequencies up to 67 MHz

DFast Access Times of 10 ns

DPackage Options Include 120-Pin Thin Quad Flat (PCB) and 132-Pin Plastic Quad Flat (PQ) Packages

The SN74ABT3611 is a high-speed, low-power BiCMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10 ns. A 64 × 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port takes place through two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices are used in parallel to create wider datapaths.

The SN74ABT3611 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The full flag (FF) and almost-full (AF) flag of the FIFO are two-stage synchronized to the port clock that writes data to its array (CLKA). The empty flag (EF) and almost-empty (AE) flag of the FIFO are two-stage synchronized to the port clock that reads data from its array.

The SN74ABT3611 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the following application reports:

•FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007)

•Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications

(literature number SCAA015)

•Metastability Performance of Clocked FIFOs (literature number SCZA004)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1998, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN74ABT3611
64	×36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E ± JULY 1992 ± REVISED APRIL 1998
																															PCB PACKAGE
																																	(TOP VIEW)
			A24		A25		A26			CC		A27		A28			A29			GND A30					A31		A32		A33		A34			A35			GND B35					B34		B33			B32			B31		B30		GND B29				B28			B27				CC		B26			B25			B24			B23
									V																																																							V
	A23		120		119		118		117			116		115			114		113		112			111			110		109		108		107			106		105			104			103		102			101			100		99		98		97			96			95			94			93			92			91					B22
			1																																																																									90
	A22		2																																																																									89					B21
	A21		3																																																																									88					GND
	GND		4																																																																									87					B20
	A20		5																																																																									86					B19
	A19		6																																																																									85					B18
	A18		7																																																																									84					B17
	A17		8																																																																									83					B16
	A16		9																																																																									82					B15
	A15		10																																																																									81					B14
	A14		11																																																																									80					B13
	A13		12																																																																									79					B12
	A12		13																																																																									78					B11
	A11		14																																																																									77					B10
	A10		15																																																																									76					GND
	GND		16																																																																									75					B9
	A9		17																																																																									74					B8
	A8		18																																																																									73					B7
	A7		19																																																																									72					VCC
	VCC		20																																																																									71					B6
	A6		21																																																																									70					B5
	A5		22																																																																									69					B4
	A4		23																																																																									68					B3
	A3		24																																																																									67					GND
	GND		25																																																																									66					B2
	A2		26																																																																									65					B1
	A1		27																																																																									64					B0
	A0		28																																																																									63					EFB
	NC		29																																																																									62					AEB
	NC		30																																																																									61					NC
			31		32		33		34			35		36			37		38		39			40			41		42		43		44			45		46			47			48		49			50			51		52		53		54			55			56			57			58			59			60

W/RA

CLKA

ENA

CSA

FFA

AFA

NC ± No internal connection

CC

PGA

PEFA

MBF2 MBA FS1 FS0

RST GND NC NC NC NC MBB

MBF1

PEFB

CC

W/RB CLKB ENB

CSB NC

V

ODD/EVEN

PGB V

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SN74ABT3611 64 ×36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCBS127E ± JULY 1992 ± REVISED APRIL 1998

PQ PACKAGE² (TOP VIEW)

					AFA			FFA			CSA ENA				CLKA		W/RA		V			PGA			PEFA		GND				MBF2			MBA			FS1			FS0			ODD/EVEN			RST			GND			NC		NC		NC		NC		MBB				MBF1			GND				PEFB			PGB V					W/RB		CLKB			ENB			CSB		NC			NC
																				CC																																																								CC
			17 16 15 14 13 12 11 10																					9			8			7				6			5			4		3				2			1 132					130						128							126			124								122						120					118
GND			18																																																	131				129							127							125				123							121						119					117
																																																																																												116
NC			19																																																																																									115
NC			20																																																																																									114
A0			21																																																																																									113
A1			22																																																																																									112
A2			23																																																																																									111
GND			24																																																																																									110
A3			25																																																																																									109
A4			26																																																																																									108
A5			27																																																																																									107
A6			28																																																																																									106
VCC			29																																																																																									105
A7			30																																																																																									104
A8			31																																																																																									103
A9			32																																																																																									102
GND			33																																																																																									101
A10			34																																																																																									100
A11			35																																																																																									99
VCC			36																																																																																									98
A12			37																																																																																									97
A13			38																																																																																									96
A14			39																																																																																									95
GND			40																																																																																									94
A15			41																																																																																									93
A16			42																																																																																									92
A17			43																																																																																									91
A18			44																																																																																									90
A19			45																																																																																									89
A20			46																																																																																									88
GND			47																																																																																									87
A21			48																																																																																									86
A22			49																																																																																									85
A23			50																																																																																									84
			51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
					V			A24			A25 A26				GND		A27		A28			A29		V			A30				A31			A32			GND			A33			A34			A35			GND			B35		B34		B33		GND			B32			B31			B30				V			B29 B28					B27		GND			B26			B25		B24			V
						CC																			CC																																															CC																					CC

NC ± No internal connection

² Uses Yamaichi socket IC51-1324-828

GND AEB EFB B0 B1 B2 GND B3 B4 B5 B6

VCC

B7

B8

B9 GND B10 B11

VCC

B12

B13

B14 GND B15 B16 B17 B18 B19 B20 GND B21 B22 B23

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SN74ABT3611 64 ×36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCBS127E ± JULY 1992 ± REVISED APRIL 1998

functional block diagram

CLKA
CSA	Port-A
W/RA	Control					MBF1
ENA	Logic
				Parity		PEFB
MBA
		Mail1		Gen/Check
RST		Register				PGB
	Device
ODD/
	Control
EVEN	RegisterInput			Parity Generation	RegisterOutput
		64	× 36
		SRAM
	36					36
A0 ± A35		Write	Read			B0 ± B35
		Pointer	Pointer
FF		Status-Flag				EF
AF		Logic				AE
	FIFO
FS0		Programmable-
		Flag
FS1
		Offset Register
PGA			Mail2
		Parity	Register
PEFA	Gen/Check					CLKB
MBF2					Port-B	CSB
					Control	W/RB
					Logic	ENB
						MBB

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SN74ABT3611

64 ×36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCBS127E ± JULY 1992 ± REVISED APRIL 1998

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

A0 ± A35

I/O

Port-A data. The 36-bit bidirectional data port for side A.

Almost-empty flag. Programmable flag synchronized to CLKB.

AE

is low when the number of words in the FIFO is less

AE

O

than or equal to the value in the offset register, X.

Almost-full flag. Programmable flag synchronized to CLKA.

is low when the number of empty locations in the FIFO

AF

AF

O

is less than or equal to the value in the offset register, X.

B0 ± B35

I/O

Port-B data. The 36-bit bidirectional data port for side B.

CLKA

I

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous

or coincident to CLKB. FF and AF are synchronized to the low-to-high transition of CLKA.

CLKB

I

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous

or coincident to CLKA. EF and AE are synchronized to the low-to-high transition of CLKB.

Port-A chip select.

must be low to enable a low-to-high transition of CLKA to read or write data on port A. The

CSA

CSA

I

A0 ± A35 outputs are in the high-impedance state when CSA is high.

Port-B chip select.

CSB

must be low to enable a low-to-high transition of CLKB to read or write data on port B. The

CSB

I

B0 ± B35 outputs are in the high-impedance state when CSB is high.

Empty flag.

EF

is synchronized to the low-to-high transition of CLKB. When

EF

is low, the FIFO is empty and reads from

its memory are disabled. Data can be read from the FIFO to its output register when EF is high. EF is forced low when

EF

O

the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded into empty FIFO

memory.

ENA

I

Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.

ENB

I

Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.

Full flag.

FF

is synchronized to the low-to-high transition of CLKA. When

FF

is low, the FIFO is full and writes to its

FF

O

memory are disabled. FF is forced low when the device is reset and is set high by the second low-to-high transition of

CLKA after reset.

Flag-offset selects. The low-to-high transition of

latches the values of FS0 and FS1, which loads one of four preset

FS1, FS0

I

RST

values into the almost-full and almost-empty offset register, X.

MBA

I

Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.

Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the

MBB

I

B0 ± B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects

the FIFO output register data for output.

Mail1 register flag.

MBF1

is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes

MBF1

O

to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B

read is selected and MBB is high. MBF1 is set high when the device is reset.

Mail2 register flag.

is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes

MBF2

MBF2

O

to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A

read is selected and MBA is high. MBF2 is set high when the device is reset.

is high and even parity is checked when

ODD/

Odd/even parity select. Odd parity is checked on each port when ODD/EVEN

I

ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled

EVEN

for a read operation.

Port-A parity error flag. When any byte applied to A0 ± A35 fails parity,

is low. Bytes are organized as A0 ± A8,

PEFA

A9 ± A17, A18 ± A26, and A27 ± A35, with the most-significant bit of each byte serving as the parity bit. The type of parity

O

checked is determined by the state of ODD/EVEN.

PEFA

(port A)

The parity trees used to check the A0 ± A35 inputs are shared by the mail2 register to generate parity if parity generation

is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having CSA low, ENA high, W/RA low,

MBA high, and PGA high,

PEFA

is forced high, regardless of the state of the A0 ± A35 inputs.

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5

SN74ABT3611 64 ×36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCBS127E ± JULY 1992 ± REVISED APRIL 1998

Terminal Functions (continued)

TERMINAL

I/O

DESCRIPTION

NAME

Port-B parity error flag. When any byte applied to terminals B0 ± B35 fails parity,

PEFB

is low. Bytes are organized as

B0 ± B8, B9 ± B17, B18 ±B26, and B27 ± B35, with the most-significant bit of each byte serving as the parity bit. The type

O

of parity checked is determined by the state of ODD/EVEN.

PEFB

(port B)

The parity trees used to check the B0 ± B35 inputs are shared by the mail1 register to generate parity if parity generation

is selected by PGB. Therefore, if a mail1 read with parity generation is set up by having CSB low, ENB high, W/RB

low, MBB high, and PGB high,

PEFB

is forced high regardless of the state of the B0 ± B35 inputs.

Port-A parity generation. Parity is generated for mail2 register reads from port A when PGA is high. The type of parity

PGA

I

generated is selected by the state of ODD/EVEN. Bytes are organized as A0 ± A8, A9 ± A17, A18± A26, and A27 ± A35.

The generated parity bits are output in the most-significant bit of each byte.

Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated

PGB

I

is selected by the state of ODD/EVEN. Bytes are organized as B0 ± B8, B9 ± B17, B18 ± B26, and B27 ± B35. The

generated parity bits are output in the most significant bit of each byte.

Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur

RST

I

while RST is low. This sets AF, MBF1, and MBF2 high and

EF,

AE, and FF low. The low-to-high transition of

RST

latches

the status of FS1 and FS0 to select

AF

and AE flag offset.

Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a

W/RA

I

low-to-high transition of CLKA. The A0 ± A35 outputs are in the high-impedance state when W/RA is high.

Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a

W/RB

I

low-to-high transition of CLKB. The B0 ± B35 outputs are in the high-impedance state when W/RB is high.

detailed description

reset

The SN74ABT3611 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. RST can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of the FIFO and forces the full flag (FF) low, the empty flag (EF) low, the almost-empty flag (AE) low, and the almost-full flag (AF) high. A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FF is set high after two low-to-high transitions of CLKA. The device must be reset after power up before data is written to its memory.

A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.

Table 1. Flag Programming

					ALMOST-FULL AND
FS1	FS0		RST		ALMOST-EMPTY FLAG
					OFFSET REGISTER (X)
H	H		↑		16
H	L		↑		12
L	H		↑		8
L	L		↑		4

FIFO write/read operation

The state of the port-A data (A0±A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0±A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0±A35 outputs are active when both CSA and W/RA are low. Data is loaded into the FIFO from the A0±A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low, and FF is high (see Table 2).

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SN74ABT3611

64

×36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCBS127E ± JULY 1992 ± REVISED APRIL 1998

FIFO write/read operation (continued)

Table 2. Port-A Enable Function Table

CSA

W/RA

ENA

MBA

CLKA

A0 ± A35 OUTPUTS

PORT FUNCTION

H

X

X

X

X

In high-impedance state

None

L

H

L

X

X

In high-impedance state

None

L

H

H

L

↑

In high-impedance state

FIFO write

L

H

H

H

↑

In high-impedance state

Mail1 write

L

L

L

L

X

Active, mail2 register

None

L

L

H

L

↑

Active, mail2 register

None

L

L

L

H

X

Active, mail2 register

None

↑

L

L

H

H

Active, mail2 register

Mail2 read (set

MBF2

high)

The port-B control signals are identical to those of port A. The state of the port-B data (B0±B35) outputs is controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0±B35 outputs are in the high-impedance state when either CSB or W/RB is high. The B0±B35 outputs are active when both CSB and W/RB are low. Data is read from the FIFO to the B0±B35 outputs by a low-to-high transition of CLKB when CSB is low, W/RB is low, ENB is high, MBB is high, and EF is high (see Table 3).

Table 3. Port-B Enable Function Table

CSB

W/RB

ENB

MBB

CLKB

B0 ± B35 OUTPUTS

PORT FUNCTION

H

X

X

X

X

In high-impedance state

None

L

H

L

X

X

In high-impedance state

None

L

H

H

L

↑

In high-impedance state

None

L

H

H

H

↑

In high-impedance state

Mail2 write

L

L

L

L

X

Active, FIFO output register

None

L

L

H

L

↑

Active, FIFO output register

FIFO read

L

L

L

H

X

Active, mail1 register

None

↑

L

L

H

H

Active, mail1 register

Mail1 read (set

MBF1

high)

The setupand hold-time constraints to the port clocks for the port-chip selects (CSA, CSB) and write/read selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select can change states during the setupand hold-time window of the cycle.

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SN74ABT3611 64 ×36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCBS127E ± JULY 1992 ± REVISED APRIL 1998

synchronized FIFO flags

Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate asynchronously to one another. FF and AF are synchronized to CLKA. EF and AE are synchronized to CLKB. Table 4 shows the relationship of the flags to the FIFO.

Table 4. FIFO Flag Operation

	NUMBER OF WORDS	SYNCHRONIZED					SYNCHRONIZED
			TO CLKB					TO CLKA
	IN THE FIFO
		EF			AE		AF			FF
	0		L		L			H		H
	1 to X		H		L			H		H
	(X + 1) to [64 ± (X + 1)]		H		H			H		H
	(64 ± X) to 63		H		H			L		H
	64		H		H			L		L

² X is the value in the almost-empty flag and almost-full flag offset register.

empty flag (EF)

The FIFO empty flag is synchronized to the port clock that reads data from its array (CLKB). When EF is high, new data can be read to the FIFO output register. When EF is low, the FIFO is empty and attempted FIFO reads are ignored.

The FIFO read pointer is incremented each time a new word is clocked to its output register. A word written to the FIFO can be read to the FIFO output register in a minimum of three port-B clock (CLKB) cycles; therefore, EF is low if a word in memory is the next data to be sent to the FIFO output register and two CLKB cycles have not elapsed since the time the word was written. The empty flag of the FIFO is set high by the second low-to-high transition of CLKB, and the new data word can be read to the FIFO output register in the following cycle.

A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 4).

full flag (FF)

The FIFO full flag is synchronized to the port clock that writes data to its array (CLKA). When FF is high, an SRAM location is free to receive new data. No memory locations are free when FF is low and attempted writes to the FIFO are ignored.

Each time a word is written to the FIFO, its write pointer is incremented. From the time a word is read from the FIFO, its previous memory location is ready to be written in a minimum of three port-A clock cycles. FF is low if less than two CLKA cycles have elapsed since the next memory write location has been read. The second low-to-high transition on CLKA after the read sets FF high and data can be written in the following clock cycle.

A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 5).

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