Texas Instruments SN74ABT2952ADBLE, SN74ABT2952ADBR, SN74ABT2952ADWR, SN74ABT2952ANT, SNJ54ABT2952AFK Datasheet

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SN54ABT2952A, SN74ABT2952A

 

 

OCTAL BUS TRANSCEIVERS AND REGISTERS

 

 

 

 

 

 

 

WITH 3-STATE OUTPUTS

 

 

 

SCBS203D ± AUGUST 1992 ± REVISED JANUARY 1998

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

State-of-the-Art EPIC-ΙΙB BiCMOS Design

SN54ABT2952A . . . JT OR W PACKAGE

 

Significantly Reduces Power Dissipation

SN74ABT2952A . . . DB, DW, PW, OR NT PACKAGE

D Two 8-Bit Back-to-Back Registers Store

 

 

 

 

(TOP VIEW)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Flowing in Both Directions

 

 

B8

 

1

24

 

VCC

 

 

 

 

 

 

Noninverting Outputs

 

 

 

 

D

 

 

B7

 

2

23

 

A8

D Typical VOLP (Output Ground Bounce) < 1 V

 

 

B6

 

3

22

 

A7

 

 

 

 

 

 

B5

 

4

21

 

A6

 

at VCC = 5 V, TA = 25°C

 

 

 

 

 

 

 

B4

 

5

20

 

A5

 

 

 

 

 

D Latch-Up Performance Exceeds 500 mA Per

 

 

 

 

 

 

B3

 

6

19

 

A4

 

 

 

 

 

JESD 17

 

 

 

 

 

 

 

B2

 

7

18

 

A3

D ESD Protection Exceeds 2000 V Per

 

 

 

 

 

 

B1

 

8

17

 

A2

 

 

 

 

 

MIL-STD-883, Method 3015; Exceeds 200 V

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

 

OEAB

 

9

16

 

 

Using Machine Model (C = 200 pF, R = 0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKAB

 

10

15

 

OEBA

D Package Options Include Plastic

 

 

 

 

 

 

 

 

 

 

 

CLKBA

 

CLKENAB

 

 

11

14

 

 

Small-Outline (DW), Shrink Small-Outline

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

12

13

 

 

CLKENBA

 

 

 

(DB), and Thin Shrink Small-Outline (PW)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Packages, Ceramic Chip Carriers (FK),

 

SN54ABT2952A . . . FK PACKAGE

 

Ceramic Flat (W) Package, and Plastic (NT)

 

 

and Ceramic (JT) DIPs

 

 

 

 

(TOP VIEW)

 

 

 

 

 

description

The 'ABT2952A transceivers consist of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or CLKENBA) input is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.

To ensure the high-impedance state during power

up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of

the resistor is determined by the current-sinking capability of the driver.

The SN54ABT2952A is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT2952A is characterized for operation from ±40°C to 85°C.

 

B6

B7

B8

NC

CC

A8

A7

 

 

V

 

B5

4

3

2

1

28 27 26

A6

5

 

 

 

 

 

25

B4

6

 

 

 

 

 

24

A5

B3

7

 

 

 

 

 

23

A4

NC

8

 

 

 

 

 

22

NC

B2

9

 

 

 

 

 

21

A3

B1

10

 

 

 

 

 

20

A2

OEAB

11

 

 

 

 

 

19

A1

 

12 13 14 15 16 17 18

 

 

CLKAB

CLKENAB

GND

NC

CLKENBA

CLKBA

OEBA

 

NC ± No internal connection

 

 

 

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1998, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

1

SN54ABT2952A, SN74ABT2952A

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS203D ± AUGUST 1992 ± REVISED JANUARY 1998

FUNCTION TABLE²

 

 

INPUTS

 

 

OUTPUT

 

 

CLKAB

 

A

B

 

CLKENAB

OEAB

 

H

X

L

X

B

³

 

 

 

 

 

 

0

 

X

H or L

L

X

B

³

 

 

 

 

 

 

0

 

L

L

L

L

 

L

L

H

H

 

X

X

H

X

Z

 

 

 

 

 

 

 

² A-to-B data flow is shown; B-to-A data flow is similar, but uses CLKENBA, CLKBA, and OEBA.

³Level of B before the indicated steady-state input conditions were established

logic symbol§

15

EN3

 

 

 

OEBA

 

 

 

13

G1

 

 

 

CLKENBA

 

 

 

14

1 C5

 

 

 

CLKBA

 

 

 

9

EN4

 

 

 

OEAB

 

 

 

11

G2

 

 

 

CLKENAB

 

 

 

10

2 C6

 

 

 

CLKAB

 

 

 

16

3

1

5D

8

A1

B1

17

6D

1

4

7

 

 

 

A2

 

 

 

B2

18

 

 

 

6

A3

 

 

 

B3

19

 

 

 

5

A4

 

 

 

B4

20

 

 

 

4

A5

 

 

 

B5

21

 

 

 

3

A6

 

 

 

B6

22

 

 

 

2

A7

 

 

 

B7

23

 

 

 

1

A8

 

 

 

B8

§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

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POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Texas Instruments SN74ABT2952ADBLE, SN74ABT2952ADBR, SN74ABT2952ADWR, SN74ABT2952ANT, SNJ54ABT2952AFK Datasheet

SN54ABT2952A, SN74ABT2952A

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS203D ± AUGUST 1992 ± REVISED JANUARY 1998

logic diagram (positive logic)

11

CLKENAB

10

CLKAB

9

OEAB

13

CLKENBA

14

 

 

CLKBA

 

 

15

 

 

OEBA

 

 

 

C1

 

16

1D

8

A1

B1

 

 

C1

 

 

1D

To Seven Other Channels

Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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