Texas Instruments SN74ABTH245DBLE, SN74ABTH245DBR, SN74ABTH245DGVR, SN74ABTH245DW, SN74ABTH245DWR Datasheet

SN54ABTH245, SN74ABTH245

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

	SCBS663D ± APRIL 1996 ± REVISED SEPTEMBER 1999
D State-of-the-Art EPIC-ΙΙB BiCMOS Design	SN54ABTH245 . . . J OR W PACKAGE
Significantly Reduces Power Dissipation	SN74ABTH245 . . . DB, DGV, DW, N, OR PW PACKAGE
	(TOP VIEW)

DLatch-Up Performance Exceeds 500 mA Per

JESD 17	DIR		1	20		VCC
D Typical VOLP (Output Ground Bounce) < 1 V	A1		2	19		OE
at VCC = 5 V, TA = 25°C	A2		3	18		B1
D Ioff and Power-Up 3-State Support Hot	A3		4	17		B2
Insertion	A4		5	16		B3
D High-Drive Outputs (±32-mA IOH, 64-mA IOL)	A5		6	15		B4
	A6	7		14		B5
D Bus Hold on Data Inputs Eliminates the
	A7					B6
		8		13
Need for External Pullup/Pulldown
	A8					B7
		9		12
Resistors
	GND	10		11		B8

D Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

SN54ABTH245 . . . FK PACKAGE

(DB), Thin Shrink Small-Outline (PW), and

(TOP VIEW)

Thin Very Small-Outline (DGV) Packages,

A2

A1

DIR V

OE

Ceramic Chip Carriers (FK), Plastic (N) and

CC

Ceramic (J) DIPs, and Ceramic Flat (W)

Package

3

2

1

20 19

A3

B1

description

4

18

A4

5

17

B2

These octal bus transceivers are designed for

A5

6

16

B3

A6

7

15

B4

asynchronous

communication

between

data

A7

8

14

B5

buses. The devices transmit data from the A bus

9

10 11 12 13

to the B bus or from the B bus to the A bus,

A8

GND

B8

B7

B6

depending

on

the

logic

level

at

the

direction-control (DIR) input. The output-enable

(OE) input can be used to disable the device so

the buses are effectively isolated.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54ABTH245 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABTH245 is characterized for operation from ±40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1999, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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SN54ABTH245, SN74ABTH245

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS663D ± APRIL 1996 ± REVISED SEPTEMBER 1999

FUNCTION TABLE

		INPUTS		OPERATION
	OE		DIR
		L	L	B data to A bus
		L	H	A data to B bus
		H	X	Isolation

logic symbol²

			19				G3
	OE
			1
DIR							3 EN1 [BA]
							3 EN2 [AB]

A1	2	18
	1	B1
		2
A2	3	17
		B2
A3	4	16
		B3
A4	5	15
		B4
A5	6	14
		B5
A6	7	13
		B6
A7	8	12
		B7
A8	9	11
		B8

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

1

DIR

19

OE

2

A1

18

B1

To Seven Other Channels

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABTH245, SN74ABTH245

OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS663D ± APRIL 1996 ± REVISED SEPTEMBER 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . .	±0.5 V to 5.5	V
Current into any output in the low state, IO: SN54ABTH245 . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 96 mA
SN74ABTH245 . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 92°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 69°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±65°C to 150°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 3)

			SN54ABTH245		SN74ABTH245		UNIT
			MIN	MAX	MIN	MAX
VCC		Supply voltage	4.5	5.5	4.5	5.5	V
VIH		High-level input voltage	2		2		V
VIL		Low-level input voltage		0.8		0.8	V
VI		Input voltage	0	VCC	0	VCC	V
IOH		High-level output current		±24		±32	mA
IOL		Low-level output current		48		64	mA
t/	v	Input transition rise or fall rate		5		5	ns/V
t/	VCC	Power-up ramp rate			200		µs/V
TA		Operating free-air temperature	±55	125	±40	85	°C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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