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SN74ACT3632 |
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512 ×36 |
×2 |
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CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY |
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SCAS224D ± JUNE 1992 ± REVISED APRIL 1998 |
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||||||
D Free-Running CLKA and CLKB Can Be |
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D IRB, ORB, |
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and |
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Flags |
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AEB, |
AFB |
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Asynchronous or Coincident |
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Synchronized by CLKB |
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D Two Independent 512 × 36 Clocked FIFOs |
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D Low-Power 0.8-mm Advanced CMOS |
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Buffering Data in Opposite Directions |
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Technology |
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D Mailbox-Bypass Register for Each FIFO |
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D Supports Clock Frequencies up to 67 MHz |
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D Programmable Almost-Full and |
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D Fast Access Times of 11 ns |
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Almost-Empty Flags |
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D Pin-to-Pin Compatible With the |
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D Microprocessor Interface Control Logic |
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SN74ACT3622 and SN74ACT3642 |
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D IRA, ORA, |
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and |
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Flags |
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D Package Options Include 120-Pin Thin |
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AEA, |
AFA |
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Synchronized by CLKA |
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Quad Flat (PCB) and 132-Pin Plastic Quad |
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Flat (PQ) Packages |
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PCB PACKAGE |
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(TOP VIEW) |
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GND CLKA |
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W/RA |
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MBF2 |
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RST1 |
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GND FS1 |
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RST2 |
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MBF1 |
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GND |
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CSB W/RB |
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CLKB |
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ENA |
CSA |
IRA |
ORA |
V |
AFA |
AEA |
MBA |
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FS0 |
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MBB |
V |
AEB |
AFB ORB |
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IRB |
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ENB |
V |
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CC |
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CC |
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CC |
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A35 |
|
120 |
119 |
118 |
117 |
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116 |
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115 |
114 |
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113 |
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112 |
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111 |
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110 |
109 |
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108 |
107 |
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106 |
105 |
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104 |
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103 |
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102 |
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101 |
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100 |
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99 |
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98 |
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97 |
96 |
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95 |
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94 |
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93 |
|
92 |
|
91 |
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B35 |
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1 |
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90 |
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A34 |
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2 |
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89 |
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B34 |
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|||||
A33 |
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3 |
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88 |
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B33 |
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|||||
A32 |
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4 |
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87 |
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B32 |
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|||||
VCC |
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5 |
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86 |
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GND |
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|||||
A31 |
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6 |
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85 |
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B31 |
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|||||
A30 |
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7 |
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84 |
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B30 |
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|||||
GND |
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8 |
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|
|
|
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|
|
|
|
|
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|
|
|
83 |
|
|
B29 |
|
|
|
|
|
|
|
|
|
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|
|
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|
|
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|
|||||
A29 |
|
9 |
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
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|
|
|
|
|
|
|
|
|
|
82 |
|
|
B28 |
|
|
|
|
|
|
|
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|
|
|
|
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|
|
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|
|||||
A28 |
|
10 |
|
|
|
|
|
|
|
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|
|
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|
|
81 |
|
|
B27 |
|
|
|
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|
|||||
A27 |
|
11 |
|
|
|
|
|
|
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|
|
80 |
|
|
B26 |
|
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|
|||||
A26 |
|
12 |
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|
|
|
|
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|
|
|
79 |
|
|
VCC |
|
|
|
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|
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|
|
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|
|||||
A25 |
|
13 |
|
|
|
|
|
|
|
|
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|
|
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|
|
|
78 |
|
|
B25 |
|
|
|
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|
|
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|
|||||
A24 |
|
14 |
|
|
|
|
|
|
|
|
|
|
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|
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|
|
77 |
|
|
B24 |
|
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|
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|
|
|
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|
|||||
A23 |
|
15 |
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
|
|
76 |
|
|
GND |
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
GND |
|
16 |
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
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|
|
|
|
|
|
|
|
75 |
|
|
B23 |
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|||||
A22 |
|
17 |
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
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|
|
|
|
|
|
|
|
74 |
|
|
B22 |
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
VCC |
|
18 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
73 |
|
|
B21 |
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|||||
A21 |
|
19 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
|
72 |
|
|
B20 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
A20 |
|
20 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
71 |
|
|
B19 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
A19 |
|
21 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
70 |
|
|
B18 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
A18 |
|
22 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
69 |
|
|
GND |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
GND |
|
23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
68 |
|
|
B17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
A17 |
|
24 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
67 |
|
|
B16 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
A16 |
|
25 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
66 |
|
|
VCC |
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A15 |
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26 |
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65 |
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B15 |
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A14 |
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27 |
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64 |
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B14 |
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A13 |
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28 |
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63 |
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B13 |
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|||||
VCC |
|
29 |
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62 |
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B12 |
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A12 |
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30 |
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61 |
|
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GND |
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31 |
32 |
33 |
34 |
35 |
36 |
37 |
38 |
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39 |
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40 |
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41 |
42 |
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43 |
44 |
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45 |
46 |
47 |
48 |
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49 |
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50 |
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51 |
52 |
53 |
54 |
55 |
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56 |
57 |
58 |
59 |
60 |
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|||||||||||||||||||||||||||||||
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GND A11 A10 |
A9 |
A8 |
A7 |
|
A6 |
|
GND |
A5 |
A4 A3 |
V |
|
A2 |
A1 |
A0 |
GND |
|
B0 |
B1 |
B2 |
|
B3 |
B4 |
B5 |
GND |
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B7 |
B8 B9 |
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B11 |
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B6 V |
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B10 |
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CC |
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CC |
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|
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
SN74ACT3632 512 ×36 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224D ± JUNE 1992 ± REVISED APRIL 1998
PQ PACKAGE² (TOP VIEW)
|
|
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|
NC |
NC |
V |
CLKB |
ENB W/RB |
CSB |
GND |
|
IRB |
ORB |
AFB |
AEB |
V |
MBF1 |
|
MBB |
RST2 |
FS1 |
GND |
FS0 |
RST1 |
MBA |
|
MBF2 |
AEA |
|
AFA |
V |
|
ORA |
IRA |
|
CSA |
W/RA |
ENA |
CLKA |
GND |
NC |
||||||||||||||||||||||||||||||||||||||||||||||||||
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CC |
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CC |
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CC |
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17 16 15 14 13 12 11 10 |
9 |
|
8 |
|
7 |
|
6 |
|
5 |
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4 |
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3 |
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2 |
|
1 132 |
130 |
|
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128 |
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126 |
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124 |
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122 |
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120 |
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118 |
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||||||||||||||||||||||||||||||||||||||||||||||
NC |
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18 |
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131 |
129 |
|
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127 |
|
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125 |
|
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123 |
|
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121 |
|
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119 |
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117 |
|
|||||||||||||||||||||||||
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116 |
||||||
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|||||||||
B35 |
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19 |
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115 |
||||
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|||||||||
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|||||||||
B34 |
|
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20 |
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114 |
||||
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|||||||||
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|||||||||
B33 |
|
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21 |
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113 |
||||
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|||||||||
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B32 |
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22 |
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112 |
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GND |
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23 |
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111 |
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|||||||||
B31 |
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24 |
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110 |
||||
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|||||||||
B30 |
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25 |
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109 |
||||
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|||||||||
B29 |
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26 |
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108 |
||||
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|||||||||
B28 |
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27 |
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107 |
||||
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|||||||||
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|||||||||
B27 |
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28 |
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106 |
||||
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|||||||||
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|||||||||
B26 |
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29 |
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105 |
||||
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|||||||||
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|||||||||
VCC |
|
|
30 |
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104 |
||||
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|||||||
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|||||||||
B25 |
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31 |
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103 |
||||
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|||||||||
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|||||||||
B24 |
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32 |
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102 |
||||
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|||||||||
GND |
|
|
33 |
|
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101 |
||||
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|||||||||
B23 |
|
|
34 |
|
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100 |
||||
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|||||||||
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|||||||||
B22 |
|
|
35 |
|
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|
99 |
||||
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|||||||||
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|||||||||
B21 |
|
|
36 |
|
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98 |
||||
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|||||||||
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|||||||||
B20 |
|
|
37 |
|
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|
97 |
||||
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|||||||||
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|||||||||
B19 |
|
|
38 |
|
|
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96 |
||||
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|||||||||
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|||||||||
B18 |
|
|
39 |
|
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95 |
||||
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|||||||||
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|
|||||||||
GND |
|
|
40 |
|
|
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94 |
||||
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|||||||||
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|||||||||
B17 |
|
|
41 |
|
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93 |
||||
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|||||||||
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|||||||||
B16 |
|
|
42 |
|
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92 |
||||
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|||||||||
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|||||||||
VCC |
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43 |
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91 |
||||
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|||||||||
B15 |
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44 |
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90 |
||||
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|||||||||
B14 |
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45 |
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89 |
||||
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|||||||||
B13 |
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46 |
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88 |
||||
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B12 |
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47 |
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87 |
||||
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|||||||||
GND |
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48 |
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86 |
||||
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|||||||||
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|||||||||
NC |
|
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49 |
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85 |
||||
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|||||||||
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|||||||||
NC |
|
|
50 |
|
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84 |
||||
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|||||||||
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|||||||||
|
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|
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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NC |
B11 |
B10 |
B9 |
B8 B7 |
V |
B6 |
GND |
B5 |
B4 |
B3 |
B2 |
B1 |
B0 |
GND |
A0 |
A1 |
A2 |
V |
A3 |
|
A4 |
A5 |
|
GND |
A6 |
A7 |
|
A8 |
|
A9 |
A10 |
A11 |
GND |
NC |
NC |
||||||||||||||||||||||||||||||||||||||||||||||||||||
|
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CC |
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CC |
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NC ± No internal connection
² Uses Yamaichi socket IC51-1324-828
NC
NC
A35
A34
A33
A32
VCC
A31
A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22
VCC
A21
A20
A19
A18 GND A17 A16 A15 A14 A13
VCC
A12
NC
2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
SN74ACT3632 512 ×36 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224D ± JUNE 1992 ± REVISED APRIL 1998
description
The SN74ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 11 ns. Two independent 512 × 36 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags, almost full (AF) and almost empty (AE) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths.
The SN74ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
The input-ready (IRA, IRB) flag and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA, AEB) flag of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the AF and AE flags of both FIFOs can be programmed from port A.
The SN74ACT3632 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the following application reports:
•FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control
(literature number SCAA007)
•Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors (literature number SCAA005)
•Metastability Performance of Clocked FIFOs (literature number SCZA004)
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
3 |
SN74ACT3632 512 ×36 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224D ± JUNE 1992 ± REVISED APRIL 1998
functional block diagram
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Mail1 |
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CLKA |
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Register |
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CSA |
Port-A |
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W/RA |
Control |
RegisterInput |
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RegisterOutput |
ENA |
Mail1 |
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Logic |
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MBA |
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SRAM |
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FIFO1, |
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RST1 |
Reset |
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Logic |
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Write |
Read |
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Pointer |
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IRA |
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Status-Flag |
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AFA |
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FIFO1 |
Logic |
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36 |
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FS0 |
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Programmable- |
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Flag |
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FS1 |
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A0 ± A35 |
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FIFO2 |
Status-Flag |
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ORA |
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AEA |
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Logic |
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Read |
Write |
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RegisterOutput |
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Pointer |
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RegisterInput |
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SRAM |
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Mail2 |
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MBF2 |
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MBF1
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ORB
AEB
B0 ± B35
IRB
AFB
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FIFO2,
Mail2
Reset RST2
Logic
CLKB
Port-B CSB
Control W/RB
Logic
ENB
MBB
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POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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SN74ACT3632 |
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512 ×36 ×2 |
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CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY |
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SCAS224D ± JUNE 1992 ± REVISED APRIL 1998 |
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Terminal Functions |
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TERMINAL |
I/O |
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DESCRIPTION |
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A0 ± A35 |
I/O |
Port-A data. The 36-bit bidirectional data port for side A. |
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O |
Port-A almost-empty flag. Programmable flag synchronized to CLKA. |
AEA |
is low when the number of words in FIFO2 |
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AEA |
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Port-B almost-empty flag. Programmable flag synchronized to CLKB. |
AEB |
is low when the number of words in FIFO1 |
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AEB |
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O |
Port-A almost-full flag. Programmable flag synchronized to CLKA. |
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AFA |
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(port A) |
FIFO1 is less than or equal to the value in the almost-full A offset register, Y1. |
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Port-B almost-full flag. Programmable flag synchronized to CLKB. |
AFB |
is low when the number of empty locations in |
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AFB |
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(port B) |
FIFO2 is less than or equal to the value in the almost-full B offset register, Y2. |
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B0 ± B35 |
I/O |
Port-B data. The 36-bit bidirectional data port for side B. |
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CLKA |
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Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous |
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or coincident to CLKB. IRA, ORA, AFA, and AEA are all synchronized to the low-to-high transition of CLKA. |
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CLKB |
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Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous |
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or coincident to CLKA. IRB, ORB, AFB, and AEB are synchronized to the low-to-high transition of CLKB. |
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Port-A chip select. |
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must be low to enable a low-to-high transition of CLKA to read or write data on port A. The |
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CSA |
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CSA |
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A0 ± A35 outputs are in the high-impedance state when CSA is high. |
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Port-B chip select. |
CSB |
must be low to enable a low-to-high transition of CLKB to read or write data on port B. The |
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CSB |
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B0 ± B35 outputs are in the high-impedance state when CSB is high. |
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ENA |
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Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A. |
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ENB |
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Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B. |
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Flag-offset selects. The low-to-high transition of a FIFO reset input latches the values of FS0 and FS1. If either FS0 |
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FS1, FS0 |
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or FS1 is high when a reset input goes high, one of three preset values is selected as the offset for the FIFO AF and |
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AE flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are low when RST1 and RST2 go high, the |
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first four writes to FIFO1 program the almost-full and almost-empty offsets for both FIFOs. |
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O |
Input-ready flag. IRA is synchronized to the low-to-high transition of CLKA. When IRA is low, FIFO1 is full and writes |
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IRA |
to its array are disabled. IRA is set low when FIFO1 is reset and is set high on the second low-to-high transition of CLKA |
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after reset. |
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Input-ready flag. IRB is synchronized to the low-to-high transition of CLKB. When IRB is low, FIFO2 is full and writes |
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IRB |
to its array are disabled. IRB is set low when FIFO2 is reset and is set high on the second low-to-high transition of CLKB |
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after reset. |
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Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the |
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MBA |
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A0 ± A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects |
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FIFO2 output-register data for output. |
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Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the |
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B0 ± B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects |
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FIFO1 output-register data for output. |
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Mail1 register flag. |
MBF1 |
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is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes |
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to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B |
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read is selected and MBB is high. MBF1 is set high when FIFO1 is reset. |
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Mail2 register flag. |
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is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes |
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MBF2 |
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to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A |
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read is selected and MBA is high. MBF2 is also set high when FIFO2 is reset. |
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Output-ready flag. ORA is synchronized to the low-to-high transition of CLKA. When ORA is low, FIFO2 is empty and |
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ORA |
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reads from its memory are disabled. Ready data is present on the output register of FIFO2 when ORA is high. ORA |
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is forced low when FIFO2 is reset and goes high on the third low-to-high transition of CLKA after a word is loaded to |
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empty memory. |
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POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
5 |
SN74ACT3632 512 ×36 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224D ± JUNE 1992 ± REVISED APRIL 1998
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Terminal Functions (Continued) |
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TERMINAL |
I/O |
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DESCRIPTION |
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NAME |
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Output-ready flag. ORB is synchronized to the low-to-high transition of CLKB. When ORB is low, FIFO1 is empty and |
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ORB |
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reads from its memory are disabled. Ready data is present on the output register of FIFO1 when ORB is high. ORB |
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is forced low when FIFO1 is reset and goes high on the third low-to-high transition of CLKB after a word is loaded to |
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empty memory. |
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FIFO1 reset. To reset FIFO1, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur |
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RST1 |
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is low. The low-to-high transition of RST1 latches the status of FS0 and FS1 for |
AFA |
and AEB offset |
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selection. FIFO1 must be reset upon power up before data is written to its RAM. |
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FIFO2 reset. To reset FIFO2, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur |
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RST2 |
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AFB |
and AEA offset |
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selection. FIFO2 must be reset upon power up before data is written to its RAM. |
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Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a |
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W/RA |
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low-to-high transition of CLKA. The A0 ± A35 outputs are in the high-impedance state when W/RA is high. |
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Port-B write/read select. A low on |
W/RB selects a write operation and a high selects a read operation on port B for a |
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W/RB |
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low-to-high transition of CLKB. The B0 ± B35 outputs are in the high-impedance state when W/RB is low. |
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detailed description
reset
The FIFO memories of the SN74ACT3632 are reset separately by taking their reset (RST1, RST2) inputs low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset inputs can switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the input-ready flag (IRA, IRB) low, the output-ready flag (ORA, ORB) low, the almost-empty flag (AEA, AEB) low, and the almost-full flag (AFA, AFB) high. Resetting a FIFO also forces the mailbox flag (MBF1, MBF2) of the parallel mailbox register high. After a FIFO is reset, its input-ready flag is set high after two clock cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory.
A low-to-high transition on a FIFO reset (RST1, RST2) input latches the value of the flag-select (FS0, FS1) inputs for choosing the almost-full and almost-empty offset programming method.
almost-empty flag and almost-full flag offset programming
Four registers in the SN74ACT3632 are used to hold the offset values for the AE and AF flags. The port-B almost-empty flag (AEB) offset register is labeled X1 and the port-A almost-empty flag (AEA) offset register is labeled X2. The port-A almost-full flag (AFA) offset register is labeled Y1 and the port-B almost-full flag (AFB) offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from port A (see Table 1).
Table 1. Flag Programming
FS1 |
FS0 |
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X1 AND Y1 REGISTERS² |
X2 AND Y2 REGISTERS³ |
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RST1 |
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RST2 |
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H |
H |
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↑ |
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X |
64 |
X |
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H |
H |
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X |
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↑ |
X |
64 |
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H |
L |
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↑ |
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X |
16 |
X |
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H |
L |
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X |
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↑ |
X |
16 |
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L |
H |
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↑ |
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X |
8 |
X |
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L |
H |
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X |
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↑ |
X |
8 |
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L |
L |
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↑ |
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↑ |
Programmed from port A |
Programmed from port A |
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² X1 register holds the offset for AEB; Y1 register holds the offset for AFA. ³ X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
6 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
SN74ACT3632 512 ×36 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224D ± JUNE 1992 ± REVISED APRIL 1998
almost-empty flag and almost-full flag offset programming (continued)
To load the AE flag and AF flag offset registers of a FIFO with one of the three preset values listed in Table 1, at least one of the flag-select inputs must be high during the low-to-high transition of its reset input. For example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be high when FIFO1 reset (RST1) returns high. Flag-offset registers associated with FIFO2 are loaded with one of the preset values in the same way with FIFO2 reset (RST2). When using one of the preset values for the flag offsets, the FIFOs can be reset simultaneously or at different times.
To program the X1, X2, Y1, and Y2 registers from port A, both FIFOs should be reset simultaneously with FS0 and FS1 low during the low-to-high transition of the reset inputs. After this reset is complete, the first four writes to FIFO1 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. Each offset register uses port-A (A8±A0) inputs, with A8 as the most-significant bit. Each register value can be programmed from 1 to 508. After all the offset registers are programmed from port A, the port-B input-ready flag (IRB) is set high and both FIFOs begin normal operation.
FIFO write/read operation
The state of the port-A data (A0±A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0±A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0±A35 outputs are active when both CSA and W/RA are low.
Data is loaded into FIFO1 from the A0±A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low, and IRA is high. Data is read from FIFO2 to the A0±A35 outputs by a low-to-high transition of CLKA when CSA is low, W/RA is low, ENA is high, MBA is low, and ORA is high (see Table 2). FIFO reads and writes on port A are independent of any concurrent port-B operation.
Table 2. Port-A Enable Function Table
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CSA |
W/RA |
ENA |
MBA |
CLKA |
A0 ± A35 OUTPUTS |
PORT FUNCTION |
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H |
X |
X |
X |
X |
In high-impedance state |
None |
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L |
H |
L |
X |
X |
In high-impedance state |
None |
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L |
H |
H |
L |
↑ |
In high-impedance state |
FIFO1 write |
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L |
H |
H |
H |
↑ |
In high-impedance state |
Mail1 write |
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L |
L |
L |
L |
X |
Active, FIFO2 output register |
None |
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L |
L |
H |
L |
↑ |
Active, FIFO2 output register |
FIFO2 read |
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L |
L |
L |
H |
X |
Active, mail2 register |
None |
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↑ |
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L |
L |
H |
H |
Active, mail2 register |
Mail2 read (set |
MBF2 |
high) |
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The port-B control signals are identical to those of port A, with the exception that the port-B write/read select (W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0±B35) outputs is controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0±B35 outputs are in the high-impedance state when either CSB is high or W/RB is low. The B0±B35 outputs are active when CSB is low and W/RB is high.
Data is loaded into FIFO2 from the B0±B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB is low, ENB is high, MBB is low, and IRB is high. Data is read from FIFO1 to the B0±B35 outputs by a low-to-high transition of CLKB when CSB is low, W/RB is high, ENB is high, MBB is low, and ORB is high (see Table 3). FIFO reads and writes on port B are independent of any concurrent port-A operation.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
7 |
SN74ACT3632 512 ×36 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224D ± JUNE 1992 ± REVISED APRIL 1998
FIFO write/read operation (continued)
Table 3. Port-B Enable Function Table
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CSB |
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W/RB |
ENB |
MBB |
CLKB |
B0 ± B35 OUTPUTS |
PORT FUNCTION |
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H |
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X |
X |
X |
X |
In high-impedance state |
None |
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L |
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L |
L |
X |
X |
In high-impedance state |
None |
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L |
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L |
H |
L |
↑ |
In high-impedance state |
FIFO2 write |
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L |
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L |
H |
H |
↑ |
In high-impedance state |
Mail2 write |
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L |
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H |
L |
L |
X |
Active, FIFO1 output register |
None |
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L |
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H |
H |
L |
↑ |
Active, FIFO1 output register |
FIFO1 read |
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L |
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H |
L |
H |
X |
Active, mail1 register |
None |
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↑ |
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L |
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H |
H |
H |
Active, mail1 register |
Mail1 read (set |
MBF1 |
high) |
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The setupand hold-time constraints to the port clocks for the port-chip selects and write/read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select may change states during the setupand hold-time window of the cycle.
When a FIFO OR flag is low, the next data word is sent to the FIFO output register automatically by the low-to-high transition of the port clock that sets the OR flag high. When the OR flag is high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the port's chip select, write/read select, enable, and mailbox select.
synchronized FIFO flags
Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asynchronously to one another. ORA, AEA, IRA, and AFA are synchronized to CLKA. ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2.
Table 4. FIFO1 Flag Operation
NUMBER OF WORDS |
SYNCHRONIZED |
SYNCHRONIZED |
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TO CLKB |
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TO CLKA |
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IN FIFO1²³ |
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ORB |
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IRA |
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AEB |
AFA |
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0 |
L |
L |
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H |
H |
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1 to X1 |
H |
L |
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H |
H |
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(X1 + 1) to [512 ± (Y1 + 1)] |
H |
H |
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H |
H |
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(512 ± Y1) to 511 |
H |
H |
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L |
H |
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512 |
H |
H |
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L |
L |
²X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of
FIFO1 or programmed from port A.
³When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
8 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
SN74ACT3632 512 ×36 ×2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS224D ± JUNE 1992 ± REVISED APRIL 1998
synchronized FIFO flags (continued)
Table 5. FIFO2 Flag Operation
NUMBER OF WORDS |
SYNCHRONIZED |
SYNCHRONIZED |
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TO CLKA |
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TO CLKB |
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IN FIFO2²³ |
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ORA |
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IRB |
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AEA |
AFB |
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0 |
L |
L |
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H |
H |
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1 to X2 |
H |
L |
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H |
H |
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(X2 + 1) to [512 ± (Y2 + 1)] |
H |
H |
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H |
H |
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(512 ± Y2) to 511 |
H |
H |
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L |
H |
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512 |
H |
H |
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L |
L |
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² X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or programmed from port A.
³When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
output-ready flags (ORA, ORB)
The OR flag of a FIFO is synchronized to the port clock that reads data from its array. When the OR flag is high, new data is present in the FIFO output register. When the OR flag is low, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored.
A FIFO read pointer is incremented each time a new word is clocked to its output register. From the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the OR flag synchronizing clock; therefore, an OR flag is low if a word in memory is the next data to be sent to the FIFO output register and three cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The OR flag of the FIFO remains low until the third low-to-high transition of the synchronizing clock occurs, simultaneously forcing the OR flag high and shifting the word to the FIFO output register.
A low-to-high transition on an OR flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 7 and 8).
input-ready flags (IRA, IRB)
The IR flag of a FIFO is synchronized to the port clock that writes data to its array. When the IR flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when the IR flag is low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is incremented. From the time a word is read from a FIFO, its previous memory location is ready to be written in a minimum of two cycles of the IR flag synchronizing clock; therefore, an IR flag is low if less than two cycles of the IR flag synchronizing clock have elapsed since the next memory write location has been read. The second low-to-high transition on the IR flag synchronizing clock after the read sets the IR flag high.
A low-to-high transition on an IR flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 9 and 10).
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
9 |