Texas Instruments SN74ABT574AN, SN74ABT574APWLE, SN74ABT574APWR, SN74ABT574ADBLE, SN74ABT574ADBR Datasheet

		SN54ABT574, SN74ABT574A
	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
					WITH 3-STATE OUTPUTS
	SCBS191C ± JANUARY 1991 ± REVISED JANUARY 1997
D State-of-the-Art EPIC-ΙΙB BiCMOS Design	SN54ABT574 . . . J OR W PACKAGE
Significantly Reduces Power Dissipation	SN74ABT574A . . . DB, DW, N, OR PW PACKAGE
D ESD Protection Exceeds 2000 V Per				(TOP VIEW)
MIL-STD-883, Method 3015; Exceeds 200 V								VCC
	OE				1	20
Using Machine Model (C = 200 pF, R = 0)
		1D			2	19		1Q
D Latch-Up Performance Exceeds 500 mA Per
		2D			3	18		2Q
JEDEC Standard JESD-17		3D			4	17		3Q
D Typical VOLP (Output Ground Bounce) < 1 V		4D			5	16		4Q
at VCC = 5 V, TA = 25°C		5D			6	15		5Q
		6D						6Q
D High-Drive Outputs (±32-mA IOH, 64-mA IOL)					7	14
		7D			8	13		7Q
D Package Options Include Plastic
		8D			9	12		8Q
Small-Outline (DW), Shrink Small-Outline
	GND				10	11		CLK
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and	SN54ABT574 . . . FK PACKAGE
Ceramic Flat (W) Package				(TOP VIEW)

description

These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops of the SN54ABT574 and SN74ABT574A are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

	2D	1D	OE	CC	1Q
				V
3D	3	2	1	20 19		2Q
	4				18
4D	5				17	3Q
5D	6				16	4Q
6D	7				15	5Q
7D	8				14	6Q
	9	10 11 12 13
	8D	GND	CLK	8Q	7Q

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT574 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT574A is characterized for operation from ±40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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SN54ABT574, SN74ABT574A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCBS191C ± JANUARY 1991 ± REVISED JANUARY 1997

FUNCTION TABLE (each flip-flop)

		INPUTS		OUTPUT
		CLK	D	Q
	OE
	L	↑	H	H
	L	↑	L	L
	L	H or L	X	Q0
	H	X	X	Z

logic symbol²

OE	1
	EN
CLK	11
	C1

		2		19
	1D		1D		1Q
		3		18
	2D				2Q
		4		17
	3D				3Q
		5		16
	4D				4Q
		6		15
	5D				5Q
		7		14
	6D				6Q
		8		13
	7D				7Q
		9		12
	8D				8Q

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

OE	1
CLK	11
		C1	19
	2	1D	1Q
1D
		To Seven Other Channels

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABT574, SN74ABT574A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCBS191C ± JANUARY 1991 ± REVISED JANUARY 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . .	±0.5 V to 5.5	V
Current into any output in the low state, IO: SN54ABT574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 96 mA
SN74ABT574A . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 115°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 128°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±65°C to 150°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2.The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.

recommended operating conditions (see Note 3)

			SN54ABT574		SN74ABT574A		UNIT
			MIN	MAX	MIN	MAX
VCC	Supply voltage		4.5	5.5	4.5	5.5	V
VIH	High-level input voltage		2		2		V
VIL	Low-level input voltage			0.8		0.8	V
VI	Input voltage		0	VCC	0	VCC	V
IOH	High-level output current			±24		±32	mA
IOL	Low-level output current			48		64	mA
t/ v	Input transition rise or fall rate	Outputs enabled		5		5	ns/V
TA	Operating free-air temperature		±55	125	±40	85	°C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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