Texas Instruments SN74ABT3613-20PCB, SN74ABT3613-20PQ, SN74ABT3613-30PCB, SN74ABT3613-30PQ, SN74ABT3613-15PCB Datasheet

SN74ABT3613 64 ×36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F ± JULY 1992 ± REVISED APRIL 1998

DLow-Power Advanced BiCMOS Technology

DFree-Running CLKA and CLKB Can Be Asynchronous or Coincident

D64 × 36 FIFO Buffering Data From Port A to

Port B

DMailbox-Bypass Registers in Each Direction

DDynamic Port-B Bus Sizing of 36 Bits (Long Word), 18 Bits (Word), and 9 Bits (Byte)

DSelection of Bigor Little-Endian Format for Word and Byte Bus Sizes

DThree Modes of Byte-Order Swapping on Port B

description

DProgrammable Almost-Full and Almost-Empty Flags

DMicroprocessor Interface Control Logic

DFF and AF Flags Synchronized by CLKA

DEF and AE Flags Synchronized by CLKB

DPassive Parity Checking on Each Port

DParity Generation Can Be Selected for Each Port

DSupports Clock Frequencies up to 67 MHz

DFast Access Times of 10 ns

DPackage Options Include 120-Pin Thin Quad Flat (PCB) and 132-Pin Quad Flat (PQ) Packages

The SN74ABT3613 is a high-speed, low-power BiCMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read-access times as fast as 10 ns. A 64 ×36 dual-port SRAM FIFO in this device buffers data from port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. FIFO data on port B can be output in 36-bit, 18-bit, and 9-bit formats, with a choice of bigor little-endian configurations. Three modes of byte-order swapping are possible with any bus-size selection. Communication between each port can bypass the FIFO via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can be selected for data read from each port.

The SN74ABT3613 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses controlled by a synchronous interface.

The full flag (FF) and almost-full (AF) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The empty flag (EF) and almost-empty (AE) flag of a FIFO are two-stage synchronized to the port clock that reads data from its array.

The SN74ABT3613 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the following application reports:

DFIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number SCAA007)

DAdvanced Bus-Matching/Byte-Swapping Features for Internetworking FIFO Applications

(literature number SCAA014)

DParity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications

(literature number SCAA015)

DInternetworking the SN74ABT3614 (literature number SCAA018)

DMetastability Performance of Clocked FIFOs (literature number SCZA004)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1998, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN74ABT3613

64 ×36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F ± JULY 1992 ± REVISED APRIL 1998

PCB PACKAGE (TOP VIEW)

			A24		A25		A26			CC		A27		A28		A29			GND		A30		A31		A32		A33		A34			A35		GND		B35		B34		B33			B32			B31		B30 GND				B29		B28			B27			CC		B26		B25		B24			B23
									V																																																			V
A23		120			119		118		117			116		115		114			113		112		111		110		109		108			107		106		105		104		103			102			101		100		99		98		97			96			95		94		93		92		91
		1																																																																		90
A22		2																																																																		89
A21		3																																																																		88
GND		4																																																																		87
A20		5																																																																		86
A19		6																																																																		85
A18		7																																																																		84
A17		8																																																																		83
A16		9																																																																		82
A15		10																																																																		81
A14		11																																																																		80
A13		12																																																																		79
A12		13																																																																		78
A11		14																																																																		77
A10		15																																																																		76
GND		16																																																																		75
A9		17																																																																		74
A8		18																																																																		73
A7		19																																																																		72
VCC		20																																																																		71
A6		21																																																																		70
A5		22																																																																		69
A4		23																																																																		68
A3		24																																																																		67
GND		25																																																																		66
A2		26																																																																		65
A1		27																																																																		64
A0		28																																																																		63
NC		29																																																																		62
NC		30																																																																		61
		31			32		33		34			35		36		37			38		39		40		41		42		43			44		45		46		47		48			49			50		51		52		53		54			55			56		57		58		59		60
			AF		FF		CSA			ENA		CLKA		W/RA		V			PGA		PEFA		MBF2		MBA FS1					FS0		ODD/EVEN		RST GND				BE SW1						SW0		SIZ1		SIZ0		MBF1		PEFB			PGB V					W/RB		CLKB		ENB		CSB			NC
																	CC																																									CC

NC ± No internal connection

B22

B21 GND B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 GND B9 B8 B7

VCC

B6

B5

B4

B3 GND B2 B1 B0 EF AE NC

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ABT3613 64 ×36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F ± JULY 1992 ± REVISED APRIL 1998

PQ PACKAGE² (TOP VIEW)

										CSA ENA					CLKA		W/RA				PGA			PEFA		GND				MBF2			MBA									ODD/EVEN						GND					SW1		SW0		SIZ1	SIZ0				MBF1			GND				PEFB				PGB V					W/RB		CLKB
					AF			FF											V																	FS1			FS0						RST						BE																																	ENB			CSB		NC			NC
																			CC																																																								CC
			17 16 15 14 13 12 11 10 9																							8			7				6			5			4			3			2			1 132					130					128							126							124					122						120						118
GND			18																																																131				129						127							125						123						121				119								117
																																																																																												116
NC			19																																																																																									115
NC			20																																																																																									114
A0			21																																																																																									113
A1			22																																																																																									112
A2			23																																																																																									111
GND			24																																																																																									110
A3			25																																																																																									109
A4			26																																																																																									108
A5			27																																																																																									107
A6			28																																																																																									106
VCC			29																																																																																									105
A7			30																																																																																									104
A8			31																																																																																									103
A9			32																																																																																									102
GND			33																																																																																									101
A10			34																																																																																									100
A11			35																																																																																									99
VCC			36																																																																																									98
A12			37																																																																																									97
A13			38																																																																																									96
A14			39																																																																																									95
GND			40																																																																																									94
A15			41																																																																																									93
A16			42																																																																																									92
A17			43																																																																																									91
A18			44																																																																																									90
A19			45																																																																																									89
A20			46																																																																																									88
GND			47																																																																																									87
A21			48																																																																																									86
A22			49																																																																																									85
A23			50																																																																																									84
			51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
					V			A24		A25 A26					GND		A27		A28		A29		V			A30				A31			A32			GND			A33			A34			A35			GND			B35		B34		B33		GND	B32				B31			B30				V			B29		B28				B27		GND				B26			B25		B24			V
						CC																		CC																																														CC																							CC

NC ± No internal connection

² Uses Yamaichi socket IC51-1324-828

GND

AE

EF

B0

B1

B2 GND B3 B4 B5 B6

VCC

B7

B8

B9 GND B10 B11

VCC

B12

B13

B14 GND B15 B16 B17 B18 B19 B20 GND B21 B22 B23

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

SN74ABT3613

64 ×36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F ± JULY 1992 ± REVISED APRIL 1998

functional block diagram

CLKA
CSA		Port-A
W/RA		Control						MBF1
ENA		Logic
								PEFB
MBA						Parity
				Mail1		Gen/Check
				Register				PGB
		RegisterInput				MatchingBusand SwappingByte	RegisterOutput
ODD/	Control		64	× 36	Parity Generation
			SRAM
RST	Device							36
EVEN
			Write	Read
	36		Pointer	Pointer
FF			Status-Flag					EF
AF			Logic					AE
							FIFO
FS0			Programmable-Flag
FS1			Offset Register					B0±B35
A0±A35
PGA					Mail2
			Parity	Register
								CLKB
PEFA			Gen/Check
								CSB
MBF2								W/RB
							Port-B	ENB
								BE
							Control
								SIZ0
							Logic
								SIZ1
								SW0
								SW1

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ABT3613

64 ×36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F ± JULY 1992 ± REVISED APRIL 1998

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

A0±A35

I/O

Port-A data. The 36-bit bidirectional data port for side A.

O

Almost-empty flag. Programmable almost-empty flag synchronized to CLKB.

AE

is low when the number of 36-bit

AE

(port B)

words in the FIFO is less than or equal to the value in offset register X.

O

Almost-full flag. Programmable almost-full flag synchronized to CLKA.

AF

is low when the number of 36-bit empty

AF

(port A)

locations in the FIFO is less than or equal to the value in offset register X.

B0±B35

I/O

Port-B data. The 36-bit bidirectional data port for side B.

Big-endian select. Selects the bytes on port B used during byte or word FIFO reads. A low on

selects the

I

BE

BE

most-significant bytes on B0±B35 for use, and a high selects the least-significant bytes.

CLKA

I

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be

asynchronous or coincident to CLKB. FF and AF are synchronized to the low-to-high transition of CLKA.

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be

CLKB

I

asynchronous or coincident to CLKA. Port-B byte swapping and data-port-sizing operations are also synchronous

to the low-to-high transition of CLKB. EF and AE are synchronized to the low-to-high transition of CLKB.

I

Port-A chip select.

CSA

must be low to enable a low-to-high transition of CLKA to read or write data on port A. The

CSA

A0±A35 outputs are in the high-impedance state when CSA is high.

Port-B chip select.

must be low to enable a low-to-high transition of CLKB to read or write data on port B. The

I

CSB

CSB

B0±B35 outputs are in the high-impedance state when CSB is high.

Empty flag.

is synchronized to the low-to-high transition of CLKB. When

is low, the FIFO is empty and reads

EF

EF

O

from its memory are disabled. Data can be read from the FIFO to the output register when EF is high. EF is forced

EF

(port B)

low when the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded into

empty FIFO memory.

ENA

I

Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.

ENB

I

Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.

O

Full flag.

FF

is synchronized to the low-to-high transition of CLKA. When

FF

is low, the FIFO is full and writes to its

FF

memory are disabled. FF is forced low when the device is reset and is set high by the second low-to-high transition

(port A)

of CLKA after reset.

FS1

I

Flag offset selects. The low-to-high transition of

RST

latches the values of FS0 and FS1, which selects one of four

FS0

preset values for the AE flag and AF flag offset.

MBA

I

Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When

the A0±A35 outputs are active, mail2 register data is output.

Mail1 register flag.

is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes

MBF1

MBF1

O

to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a

port-B read is selected and both SIZ1 and SIZ0 are high. MBF1 is set high when the device is reset.

Mail2 register flag.

MBF2

is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes

MBF2

O

to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a

port-A read is selected and MBA is high. MBF2 is set high when the device is reset.

is high and even parity is checked when

Odd/even parity select. Odd parity is checked on each port when ODD/EVEN

ODD/EVEN

I

ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled

for a read operation.

Port-A parity error flag. When any byte applied to terminals A0±A35 fails parity,

PEFA

is low. Bytes are organized

as A0±A8, A9±A17, A18±A26, and A27±A35, with the most-significant bit of each byte serving as the parity bit. The

O

type of parity checked is determined by the state of ODD/EVEN.

PEFA

(port A)

The parity trees used to check the A0±A35 inputs are shared by the mail2 register to generate parity if parity

generation is selected by PGA; therefore, if a mail2 read with parity generation is set up by having CSA low, ENA

high, W/RA low, MBA high, and PGA high, the PEFA flag is forced high, regardless of the state of the A0±A35 inputs.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

SN74ABT3613

64 ×36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F ± JULY 1992 ± REVISED APRIL 1998

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

Port-B parity error flag. When any valid byte applied to terminals B0±B35 fails parity,

is low. Bytes are

PEFB

organized as B0±B8, B9±B17, B18±B26, and B27±B35 with the most-significant bit of each byte serving as the parity

bit. A byte is valid when it is used by the bus size selected for port B. The type of parity checked is determined by

O

the state of ODD/EVEN.

PEFB

(port B)

The parity trees used to check the B0±B35 inputs are shared by the mail1 register to generate parity if parity

generation is selected by PGB; therefore, if a mail1 read with parity generation is set up by having CSB low, ENB

high, W/RB low, SIZ1 and SIZ0 high, and PGB high, the PEFB flag is forced high, regardless of the state of the

B0±B35 inputs.

Port-A parity generation. Parity is generated for data reads from the mail2 register when PGA is high. The type of

PGA

I

parity generated is selected by the state of ODD/EVEN. Bytes are organized as A0±A8, A9±A17, A18±A26, and

A27±A35. The generated parity bits are output in the most-significant bit of each byte.

Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity

PGB

I

generated is selected by the state of ODD/EVEN. Bytes are organized as B0±B8, B9±B17, B18±B26, and B27±B35.

The generated parity bits are output in the most-significant bit of each byte.

Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur

RST

I

while

RST

is low. This sets the AF,

MBF1,

and MBF2 flags high and the EF, AE, and FF flags low. The low-to-high

transition of

RST

latches the status of the FS1 and FS0 inputs to select AF flag and AE flag offset.

SIZ0

I

Port-B bus size selects. The low-to-high transition of CLKB latches the states of SIZ0, SIZ1, and

BE,

and the following

low-to-high transition of CLKB implements the latched states as a port-B bus size. Port-B bus sizes can be long word,

SIZ1

(port B)

word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox registers for a port-B 36-bit write or read.

SW0

I

Port-B byte swap selects. At the beginning of each long-word FIFO read, one of four modes of byte-order swapping

is selected by SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order

SW1

(port B)

swapping is possible with any bus-size selection.

I

Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a

W/RA

low-to-high transition of CLKA. The A0±A35 outputs are in the high-impedance state when W/RA is high.

I

Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a

W/RB

low-to-high transition of CLKB. The B0±B35 outputs are in the high-impedance state when W/RB is high.

detailed description

reset

The SN74ABT3613 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces FF low, EF low, AE low, and the AF high. A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FF is set high after two low-to-high transitions of CLKA. The device must be reset after power up before data is written to its memory.

A low-to-high transition on the RST input loads the AF and AE offset register (X) with the value selected by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.

Table 1. Flag Programming

							AF/AE FLAG
	FS1	FS0		RST
						OFFSET REGISTER (X)
	H	H		↑		16
	H	L		↑		12
	L	H		↑		8
	L	L		↑		4

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ABT3613 64 ×36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F ± JULY 1992 ± REVISED APRIL 1998

FIFO write/read operation

The state of the port-A data (A0±A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0±A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0±A35 outputs are active when both CSA and W/RA are low. Data is loaded into the FIFO from the A0±A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low, and FFA is high (see Table 2).

Table 2. Port-A Enable Function Table

CSA	W/RA	ENA	MBA	CLKA	A0±A35 OUTPUTS	PORT FUNCTION
H	X	X	X	X	In high-impedance state	None
L	H	L	X	X	In high-impedance state	None
L	H	H	L	↑	In high-impedance state	FIFO write
L	H	H	H	↑	In high-impedance state	Mail1 write
L	L	L	L	X	Active, mail2 register	None
L	L	H	L	↑	Active, mail2 register	None
L	L	L	H	X	Active, mail2 register	None
				↑
L	L	H	H		Active, mail2 register	Mail2 read (set	MBF2	high)

The state of the port-B data (B0±B35) outputs is controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0±B35 outputs are in the high-impedance state when either CSB or W/RB is high. The B0±B35 outputs are active when both CSB and W/RB are low. Data is read from the FIFO to the B0±B35 outputs by a low-to-high transition of CLKB when CSB is low, W/RB is low, ENB is high, EFB is high, and either SIZ0 or SIZ1 is low (see Table 3).

Table 3. Port-B Enable Function Table

CSB	W/RB	ENB	SIZ1, SIZ0	CLKB	B0±B35 OUTPUTS	PORT FUNCTION
H	X	X	X	X	In high-impedance state	None
L	H	L	X	X	In high-impedance state	None
L	H	H	One, both low	↑	In high-impedance state	None
L	H	H	Both high	↑	In high-impedance state	Mail2 write
L	L	L	One, both low	X	Active, FIFO output register	None
L	L	H	One, both low	↑	Active, FIFO output register	FIFO read
L	L	L	Both high	X	Active, mail1 register	None
				↑
L	L	H	Both high		Active, mail1 register	Mail1 read (set	MBF1	high)

The setupand hold-time constraints to the port clocks for the port-chip selects (CSA, CSB) and write/read selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port chip select and write/read select can change states during the setupand hold-time window of the cycle.

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7

SN74ABT3613

64 ×36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F ± JULY 1992 ± REVISED APRIL 1998

synchronized FIFO flags

Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously to one another. FF and AF are synchronized to CLKA. EF and AE are synchronized to CLKB. Table 4 shows the relationship of each port flag to the level of FIFO fill.

Table 4. FIFO Flag Operation

NUMBER OF 36-BIT

SYNCHRONIZED

SYNCHRONIZED

TO CLKB

TO CLKA

WORDS IN THE FIFO²

EF

AE

AF

FF

0

L

L

H

H

1 to X

H

L

H

H

(X + 1) to [64 ± (X + 1)]

H

H

H

H

(64 ± X) to 63

H

H

L

H

64

H

H

L

L

² X is the value in the AE flag and AF flag offset register.

empty flag (EF)

The FIFO EF is synchronized to the port clock that reads data from its array (CLKB). When the empty flag is high, new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and attempted FIFO reads are ignored. When reading the FIFO with a byte or word size on port B, EF is set low when the fourth byte or second word of the last long word is read.

The FIFO read pointer is incremented each time a new word is clocked to the output register. A word written to the FIFO can be read to the FIFO output register in a minimum of three port-B clock (CLKB) cycles. An EF is low if a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The FIFO EF is set high by the second low-to-high transition of CLKB and the new data word can be read to the FIFO output register in the following cycle.

A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 9).

full flag (FF)

The FIFO FF is synchronized to the port clock that writes data to its array (CLKA). When FF is high, a memory location is free in the SRAM to receive new data. No memory locations are free when FF is low and attempted writes to the FIFO are ignored.

Each time a word is written to the FIFO, the write pointer is incremented. From the time a word is read from the FIFO, the previous memory location is ready to be written in a minimum of three CLKA cycles. FF is low if fewer than two CLKA cycles have elapsed since the next memory-write location has been read. The second low-to-high transition on the FF synchronizing clock after the read sets the FF high and data can be written in the following clock cycle.

A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 10).

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ABT3613 64 ×36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F ± JULY 1992 ± REVISED APRIL 1998

almost-empty flag (AE)

The FIFO AE flag is synchronized to the port clock that reads data from its array (CLKB). The almost-empty state is defined by the value of the AF and AE offset register (X). This register is loaded with one of four preset values during a device reset (see reset). An AE flag is low when the FIFO contains X or fewer long words in memory and is high when the FIFO contains (X + 1) or more long words.

Two low-to-high transitions of CLKB are required after a FIFO write for the AE flag to reflect the new level of fill; therefore, the AE flag of a FIFO containing (X + 1) or more long words remains low if two CLKB cycles have not elapsed since the write that filled the memory to the (X + 1) level. An AE flag is set high by the second low-to-high transition of CLKB after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of CLKB begins the first synchronization cycle if it occurs at time tsk2, or greater, after the write that fills the FIFO to (X + 1) long words. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 11).

almost-full flag (AF)

The FIFO AF flag is synchronized to the port clock that writes data to its array (CLKA). The almost-full state is defined by the value of the AF and AE offset register (X). This register is loaded with one of four preset values during a device reset (see reset). An AF flag is low when the FIFO contains (64 ± X) or more long words in memory and is high when the FIFO contains [64 ± (X + 1)] or less long words.

Two low-to-high transitions of CLKA are required after a FIFO read for the AF flag to reflect the new level of fill; therefore, the AF flag of a FIFO containing [64 ± (X + 1)] or fewer words remains low if two CLKA cycles have not elapsed since the read that reduced the number of long words in memory to [64 ± (X + 1)]. An AF flag is set high by the second low-to-high transition of CLKA after the FIFO read that reduces the number of long words in memory to [64 ± (X + 1)]. A low-to-high transition of CLKA begins the first synchronization cycle if it occurs at time tsk2, or greater, after the read that reduces the number of long words in memory to [64 ± (X + 1)]. Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 12).

mailbox registers

Two 36-bit bypass registers (mail1, mail2) are on board the SN74ABT3613 to pass command and control information between port A and port B without putting it in queue. A low-to-high transition on CLKA writes A0±A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA, and MBA is high. A low-to-high transition on CLKB writes B0±B35 data to the mail2 register when a port-B write is selected by (CSB, W/RB, and ENB) and both SIZ0 and SIZ1 are high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while the mail flag is low.

When the port-B data outputs (B0±B35) are active, the data on the bus comes from the FIFO output register when either one or both SIZ1 and SIZ0 are low and from the mail1 register when both SIZ1 and SIZ0 are high. The mail1 register flag (MBF1) is set high by a rising CLKB edge when a port-B read is selected by CSB, W/RB, and ENB, and both SIZ1 and SIZ0 are high. The mail2 register flag (MBF2) is set high by a rising CLKA edge when a port-A read is selected by CSA, W/RA, and ENA and MBA is high. The data in the mail register remains intact after it is read and changes only when new data is written to the register.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

9

SN74ABT3613

64 ×36 CLOCKED FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F ± JULY 1992 ± REVISED APRIL 1998

dynamic bus sizing

The port-B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from the FIFO. Wordand byte-size bus selections can utilize the most-significant bytes of the bus (big endian) or least-significant bytes of the bus (little endian). Port-B bus size can be changed dynamically and synchronous to CLKB to communicate with peripherals of various bus widths.

The levels applied to the port-B bus-size select (SIZ0, SIZ1) inputs and the big-endian select (BE) input are stored on each CLKB low-to-high transition. The stored port-B bus-size selection is implemented by the next rising edge on CLKB according to Figure 1.

Only 36-bit long-word data is written to or read from the FIFO memory on the SN74ABT3613. Bus-matching operations are done after data is read from the FIFO RAM. Port-B bus sizing does not apply to mail-register operations.

A35

A27

A26

A18

A17

A9

A8

A0

BYTE ORDER ON PORT A:

A

B

C

D

Write to FIFO

B35

B27

B26

B18

B17

B9

B8

B0

SIZ1

SIZ0

BE

Read From FIFO

A

B

C

D

X

L

L

(a) LONG-WORD SIZE

B35

B27

B26

B18

B17

B9

B8

B0

BE

SIZ1

SIZ0

A

B

1st: Read From FIFO

L

L

H

B35

B27

B26

B18

B17

B9

B8

B0

2nd: Read From FIFO

C

D

(b) WORD SIZE ± BIG ENDIAN

B35

B27

B26

B18

B17

B9

B8

B0

BE

SIZ1

SIZ0

C

D

1st: Read From FIFO

H

L

H

B35

B27

B26

B18

B17

B9

B8

B0

2nd: Read From FIFO

A

B

(c) WORD SIZE ± LITTLE ENDIAN

Figure 1. Dynamic Bus Sizing

10	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265