Texas Instruments SN74ACT534DBLE, SN74ACT534DBR, SN74ACT534DW, SN74ACT534DWR, SN74ACT534N Datasheet

SN54ACT534, SN74ACT534

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS556B ± NOVEMBER 1995 ± REVISED JANUARY 2000

D Inputs Are TTL-Voltage Compatible

SN54ACT534 . . . J OR W PACKAGE

D 3-State Inverting Outputs Drive Bus Lines

SN74ACT534 . . . DB, DW, N, OR PW PACKAGE

(TOP VIEW)

Directly

D Full Parallel Access for Loading

1

20

VCC

OE

D EPIC (Enhanced-Performance Implanted

2

19

8Q

1Q

1D

3

18

8D

CMOS) 1- m Process

2D

4

17

7D

D Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

2Q

5

16

7Q

6

15

(DB), and Thin Shrink Small-Outline (PW)

3Q

6Q

Packages, Ceramic Chip Carriers (FK) and

3D

7

14

6D

Flatpacks (W), and Standard Plastic (N) and

4D

8

13

5D

9

12

Ceramic (J) DIPs

4Q

5Q

GND

10

11

CLK

description

These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input,

the Q outputs are set to the complements of the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

SN54ACT534 . . . FK PACKAGE

(TOP VIEW)

	1D	1Q		CC	8Q
			OE V
2D	3	2	1	20 19		8D
	4				18
2Q	5				17	7D
3Q	6				16	7Q
3D	7				15	6Q
4D	8	10 11			14	6D
	9			12 13
	4Q	GND	CLK	5Q	5D

OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54ACT534 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ACT534 is characterized for operation from ±40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2000, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN54ACT534, SN74ACT534

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS556B ± NOVEMBER 1995 ± REVISED JANUARY 2000

			FUNCTION TABLE
			(each flip-flop)
			INPUTS			OUTPUT
			CLK	D			Q
		OE
		L	↑	H			L
		L	↑	L			H
		L	H or L	X
							Q	0
		H	X	X			Z
logic symbol²				logic diagram (positive logic)

1	EN
OE
11	C1
CLK
3	1D	1	2
1D			1Q
4			5
2D			2Q
7			6
3D			3Q
8			9
4D			4Q
13			12
5D			5Q
14			15
6D			6Q
17			16
7D			7Q
18			19
8D			8Q

1
OE
11
CLK
	C1	2
3	1D	1Q
1D
	To Seven Other Channels

²This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 69°C/W
PW package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . ±65°C to 150°C

³ Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265