Texas Instruments SN74ABT841ADBLE, SN74ABT841ADBR, SN74ABT841ADW, SN74ABT841ADWR, SN74ABT841ANT Datasheet

		SN54ABT841, SN74ABT841A
	10-BIT BUS-INTERFACE D-TYPE LATCHES
					WITH 3-STATE OUTPUTS
	SCBS196D ± FEBRUARY 1991 ± REVISED MAY 1997
D State-of-the-Art EPIC-ΙΙB BiCMOS Design	SN54ABT841 . . . JT OR W PACKAGE
Significantly Reduces Power Dissipation	SN74ABT841A . . . DB, DW, NT, OR PW PACKAGE
D ESD Protection Exceeds 2000 V Per				(TOP VIEW)
MIL-STD-883, Method 3015; Exceeds 200 V								VCC
	OE				1	24
Using Machine Model (C = 200 pF, R = 0)
		1D			2	23		1Q
D Latch-Up Performance Exceeds 500 mA Per		2D			3	22		2Q
JEDEC Standard JESD-17		3D			4	21		3Q
D Typical VOLP (Output Ground Bounce) < 1 V		4D			5	20		4Q
at VCC = 5 V, TA = 25°C		5D			6	19		5Q
D High-Impedance State During Power Up		6D			7	18		6Q
		7D			8	17		7Q
and Power Down
		8D			9	16		8Q
D High-Drive Outputs (±32-mA IOH, 64-mA IOL)
		9D			10	15		9Q
D Package Options Include Plastic	10D				11	14		10Q
Small-Outline (DW), Shrink Small-Outline	GND				12	13		LE
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),	SN54ABT841 . . . FK PACKAGE
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs				(TOP VIEW)

description

The SN54ABT841 and SN74ABT841A 10-bit latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The ten transparent D-type latches provide true data at their outputs.

A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

	2D	1D	OE	NC	CC	1Q	2Q
					V
	4	3	2	1	28 27 26
3D	5						25	3Q
4D	6						24	4Q
5D	7						23	5Q
NC	8						22	NC
6D	9						21	6Q
7D	10						20	7Q
8D	11						19	8Q
	12 13 14			15 16 17 18
	9D	10D	GND	NC	LE	10Q	9Q

NC ± No internal connection

OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT841 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT841A is characterized for operation from ±40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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SN54ABT841, SN74ABT841A

10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

SCBS196D ± FEBRUARY 1991 ± REVISED MAY 1997

FUNCTION TABLE

		INPUTS		OUTPUT
		LE	D	Q
	OE
	L	H	H	H
	L	H	L	L
	L	L	X	Q0
	H	X	X	Z

logic symbol²

		1			EN
	OE
13
	LE				C1
2								23
	1D				1D				1Q
3								22
	2D								2Q
4								21
	3D								3Q
5								20
	4D								4Q
6								19
	5D								5Q
7								18
	6D								6Q
8								17
	7D								7Q
								16
9									8Q
	8D
10								15
	9D								9Q
11								14
10D									10Q

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

logic diagram (positive logic)

OE	1
LE	13
		C1	23
1D	2	1D	1Q
		To Seven Other Channels

Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABT841, SN74ABT841A 10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

SCBS196D ± FEBRUARY 1991 ± REVISED MAY 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . .	±0.5 V to 5.5	V
Current into any output in the low state, IO: SN54ABT841 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 96 mA
SN74ABT841A . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 104°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 81°C/W
NT package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 120°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±65°C to 150°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2.The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.

recommended operating conditions (see Note 3)

			SN54ABT841		SN74ABT841A		UNIT
			MIN	MAX	MIN	MAX
VCC		Supply voltage	4.5	5.5	4.5	5.5	V
VIH		High-level input voltage	2		2		V
VIL		Low-level input voltage		0.8		0.8	V
VI		Input voltage	0	VCC	0	VCC	V
IOH		High-level output current		±24		±32	mA
IOL		Low-level output current		48		64	mA
t/	v	Input transition rise or fall rate		5		5	ns/V
t/	VCC	Power-up ramp rate	200		200		µs/V
TA		Operating free-air temperature	±55	125	±40	85	°C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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