Texas Instruments SN74ACT564DBR, SN74ACT564DW, SN74ACT564DWR, SN74ACT564N, SN74ACT564PWLE Datasheet

				SN54ACT564, SN74ACT564
	OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
				WITH 3-STATE OUTPUTS
	SCAS549A ± NOVEMBER 1995 ± REVISED MAY 1996
D Inputs Are TTL-Voltage Compatible	SN54ACT564 . . . J OR W PACKAGE
D EPIC (Enhanced-Performance Implanted	SN74ACT564 . . . DB, DW, N, OR PW PACKAGE
				(TOP VIEW)
CMOS) 1- m Process
D 3-State Inverted Outputs Drive Bus Lines						VCC
		OE		1	20
Directly
		1D		2	19	1Q
		2D
D Flow-Through Architecture to Optimize				3	18	2Q
PCB Layout		3D
				4	17	3Q
		4D
D Full Parallel Access for Loading				5	16	4Q
		5D
D Package Options Include Plastic				6	15	5Q
		6D
				7	14	6Q
Small-Outline (DW), Shrink Small-Outline
		7D
				8	13	7Q
(DB), Thin Shrink Small-Outline (PW),
		8D
Ceramic Chip Carriers (FK) and				9	12	8Q
	GND			10	11	CLK
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs

description

SN54ACT564 . . . FK PACKAGE

(TOP VIEW)

The 'ACT564 are octal D-type edge-triggered flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the complements of the logic levels set up at the data (D) inputs.

	2D	1D	OE	CC	1Q
				V
3D	3	2	1	20 19		2Q
	4				18
4D	5				17	3Q
5D	6				16	4Q
6D	7				15	5Q
7D	8				14	6Q
	9	10 11 12 13
	8D	GND	CLK	8Q	7Q

A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54ACT564 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ACT564 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (each flip-flop)

		INPUTS		OUTPUT
		CLK	D		Q
	OE
	L	↑	H		L
	L	↑	L		H
	L	H or L	X
					Q	0
	H	X	X		Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1996, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN54ACT564, SN74ACT564

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS549A ± NOVEMBER 1995 ± REVISED MAY 1996

logic symbol²

logic diagram (positive logic)

1	EN				1
OE				OE
11	C1
CLK					11
				CLK
2			19
	1D	1
1D			1Q
3			18			C1
2D			2Q				19	1Q
4			17	1D	2	1D
3D			3Q
5			16
4D			4Q
6			15
5D			5Q
7			14
6D			6Q			To Seven Other Channels
8			13
7D			7Q
9			12
8D			8Q

²This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . ±200 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . .	. . . . . . . . . . . . 0.6 W
DW package . . . . .	. . . . . . . . . . . . 1.6 W
N package . . . . . . .	. . . . . . . . . . . . 1.3 W
PW package . . . . .	. . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . ±65°C to 150°C

³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2.The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265