Texas Instruments SN74ABT2244ADBLE, SN74ABT2244ADBR, SN74ABT2244ADW, SN74ABT2244ADWR, SN74ABT2244AN Datasheet

		SN54ABT2244A, SN74ABT2244A
		OCTAL BUFFERS AND LINE/MOS DRIVERS
				WITH 3-STATE OUTPUTS
			SCBS106E ± JANUARY 1991 ± REVISED MAY 1997
D Output Ports Have Equivalent 25-Ω Series		SN54ABT2244A . . . J OR W PACKAGE
	Resistors, So No External Resistors Are	SN74ABT2244A . . . DB, DW, N, OR PW PACKAGE
	Required		(TOP VIEW)
D ESD Protection Exceeds 2000 V Per			1OE	1		20	VCC
	MIL-STD-883, Method 3015; Exceeds 200 V
			1A1	2		19	2OE
	Using Machine Model (C = 200 pF, R = 0)
			2Y4	3		18	1Y1
D Latch-Up Performance Exceeds 500 mA Per
			1A2	4		17	2A4
	JEDEC Standard JESD-17		2Y3	5		16	1Y2
D	State-of-the-Art EPIC-ΙΙB BiCMOS Design		1A3	6		15	2A3
	Significantly Reduces Power Dissipation		2Y2	7		14	1Y3
D Typical VOLP (Output Ground Bounce) < 1 V			1A4	8		13	2A2
			2Y1				1Y4
	at VCC = 5 V, TA = 25°C			9		12
D High-Impedance State During Power Up			GND	10		11	2A1
	and Power Down
D Package Options Include Plastic		SN54ABT2244A . . . FK PACKAGE
	Small-Outline (DW), Shrink Small-Outline		(TOP VIEW)
			2Y4	1A1	1OE	V	2OE
	(DB), and Thin Shrink Small-Outline (PW)
						CC
	Packages, Ceramic Chip Carriers (FK),
	Plastic (N) and Ceramic (J) DIPs, and		3	2	1	20 19
	Ceramic Flat (W) Packages	1A2						1Y1
			4				18
description		2Y3	5				17	2A4
		1A3	6				16	1Y2
	These octal buffers and line drivers are designed	2Y2	7				15	2A3
		1A4	8				14	1Y3
	specifically to improve both the performance and
			9	10 11 12 13
	density of 3-state memory address drivers, clock		2Y1	GND	2A1	1Y4	2A2
	drivers, and bus-oriented receivers and
	transmitters. Together with the SN54ABT2240,
	SN74ABT2240A, and 'ABT2241, these devices
	provide the choice of selected combinations of
	inverting and noninverting outputs, symmetrical
	active-low output-enable (OE) inputs, and
	complementary OE and OE inputs. These devices
	feature high fan-out and improved fan-in.
	The outputs, which are designed to sink up to 12 mA, include equivalent 25-Ω series resistors to reduce
	overshoot and undershoot.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT2244A is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT2244A is characterized for operation from ±40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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SN54ABT2244A, SN74ABT2244A

OCTAL BUFFERS AND LINE/MOS DRIVERS

WITH 3-STATE OUTPUTS

SCBS106E ± JANUARY 1991 ± REVISED MAY 1997

FUNCTION TABLE (each buffer)

	INPUTS		OUTPUT
		A	Y
	OE
	L	H	H
	L	L	L
	H	X	Z

logic symbol²

			1									19
1OE				EN						2OE				EN
			2					18		11							9
				1										1
1A1									1Y1	2A1								2Y1
			4				16			13							7
1A2									1Y2	2A2								2Y2
			6				14			15							5
1A3									1Y3	2A3								2Y3
			8				12			17							3
1A4									1Y4	2A4								2Y4

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

1		19
1OE		2OE
2	18	11	9
1A1	1Y1	2A1	2Y1
4	16	13	7
1A2	1Y2	2A2	2Y2
6	14	15	5
1A3	1Y3	2A3	2Y3
8	12	17	3
1A4	1Y4	2A4	2Y4

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABT2244A, SN74ABT2244A

OCTAL BUFFERS AND LINE/MOS DRIVERS

WITH 3-STATE OUTPUTS

SCBS106E ± JANUARY 1991 ± REVISED MAY 1997

schematic of Y outputs

VCC

Output

GND

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . .	±0.5 V to 5.5	V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 30 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 115°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 128°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±65°C to 150°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2.The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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