SN54ACT563, SN74ACT563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SCAS550A ± NOVEMBER 1995 ± REVISED 1996
D D
Inputs Are TTL-Voltage Compatible
3-State Inverted Outputs Drive Bus Lines
Directly
SN54ACT563 . . . J OR W PACKAGE SN74ACT563 . . . DB, DW, N, OR PW PACKAGE (TOP VIEW)
D Flow-Through Architecture to Optimize |
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VCC |
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OE |
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20 |
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PCB Layout |
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1D |
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2 |
19 |
1Q |
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D EPIC (Enhanced-Performance Implanted |
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2D |
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3 |
18 |
2Q |
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3D |
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4 |
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3Q |
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CMOS) 1- m Process |
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4D |
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D Package Options Include Plastic |
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5 |
16 |
4Q |
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5D |
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Small-Outline (DW), Shrink Small-Outline |
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6 |
15 |
5Q |
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6D |
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(DB), Thin Shrink Small-Outline (PW), |
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7 |
14 |
6Q |
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7D |
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Ceramic Chip Carriers (FK) and |
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8 |
13 |
7Q |
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8D |
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Flatpacks (W), and Standard Plastic (N) and |
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9 |
12 |
8Q |
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Ceramic (J) DIPs |
GND |
10 |
11 |
LE |
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description
The 'ACT563 are octal D-type transparent latches with 3-state outputs. When the latch-enable (LE) input is high, the Q outputs are set to the complements of the data (D) inputs. When LE is taken low, the Q outputs are latched at the inverse logic levels set up at the D inputs.
A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines without interface or pullup components.
SN54ACT563 . . . FK PACKAGE
(TOP VIEW)
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2D |
1D |
OE |
CC |
1Q |
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V |
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3D |
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2 |
1 |
20 19 |
2Q |
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4 |
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18 |
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4D |
5 |
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17 |
3Q |
5D |
6 |
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16 |
4Q |
6D |
7 |
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15 |
5Q |
7D |
8 |
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14 |
6Q |
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9 |
10 11 12 13 |
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8D |
GND |
CLK |
8Q |
7Q |
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OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ACT563 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ACT563 is characterized for operation from ±40°C to 85°C.
FUNCTION TABLE (each latch)
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INPUTS |
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OUTPUT |
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LE |
D |
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Q |
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OE |
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L |
H |
H |
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L |
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L |
H |
L |
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H |
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L |
L |
X |
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Q |
0 |
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H |
X |
X |
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Z |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
SN54ACT563, SN74ACT563
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS550A ± NOVEMBER 1995 ± REVISED 1996
logic symbol² |
logic diagram (positive logic) |
1 |
EN |
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1 |
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OE |
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OE |
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11 |
C1 |
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LE |
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11 |
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LE |
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2 |
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19 |
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1D |
1 |
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1D |
1Q |
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3 |
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18 |
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C1 |
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2D |
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2Q |
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19 |
1Q |
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4 |
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17 |
1D |
2 |
1D |
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3D |
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3Q |
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5 |
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16 |
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4D |
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4Q |
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6 |
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15 |
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5D |
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5Q |
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7 |
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14 |
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6D |
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6Q |
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To Seven Other Channels |
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8 |
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13 |
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7D |
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7Q |
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9 |
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12 |
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8D |
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8Q |
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²This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . ±0.5 V to 7 |
V |
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.5 V to VCC + 0.5 |
V |
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.5 V to VCC + 0.5 |
V |
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±20 mA |
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Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±20 mA |
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Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . ±50 mA |
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Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . ±200 mA |
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Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . |
. . . . . . . . . . . . 0.6 W |
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DW package . . . . . |
. . . . . . . . . . . . 1.6 W |
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N package . . . . . . . |
. . . . . . . . . . . . 1.3 W |
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PW package . . . . . |
. . . . . . . . . . . . 0.7 W |
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Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . ±65°C to 150°C |
³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2.The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.
2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |