Texas Instruments SN74AC564DBLE, SN74AC564DBR, SN74AC564DW, SN74AC564DWR, SN74AC564N Datasheet

SN54AC564, SN74AC564

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS551A ± NOVEMBER 1995 ± REVISED MAY 1996

D 3-State Inverting Outputs Drive Bus Lines	SN54AC564 . . . J OR W PACKAGE
Directly	SN74AC564 . . . DB, DW, N, OR PW PACKAGE
D Full Parallel Access for Loading				(TOP VIEW)
D Flow-Through Architecture to Optimize						VCC
		OE		1	20
PCB Layout
		1D		2	19	1Q
D EPIC (Enhanced-Performance Implanted		2D
				3	18	2Q
		3D
				4	17	3Q
CMOS) 1- m Process		4D
D Package Options Include Plastic				5	16	4Q
		5D
Small-Outline (DW), Shrink Small-Outline				6	15	5Q
		6D
(DB), Thin Shrink Small-Outline (PW),				7	14	6Q
		7D
Ceramic Chip Carriers (FK) and				8	13	7Q
		8D
Flatpacks (W), and Standard Plastic (N) and				9	12	8Q
Ceramic (J) DIPs	GND			10	11	CLK

description

SN54ACT564 . . . FK PACKAGE

(TOP VIEW)

The 'AC564 are octal D-type edge-triggered					CC
flip-flops that feature inverting 3-state outputs		2D	1D	OE		1Q
designed specifically for driving highly capacitive					V
or relatively low-impedance loads. They are	3D	3	2	1	20 19		2Q
particularly suitable for implementing buffer		4				18
registers, I/O ports, bidirectional bus drivers, and	4D	5				17	3Q
working registers.	5D	6				16	4Q
On the positive transition of the clock (CLK) input,	6D	7				15	5Q
	7D	8				14	6Q
the Q outputs are set to the inverse logic levels set
		9	10 11 12 13
up at the data (D) inputs.		8D	GND	CLK	8Q	7Q
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.

OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54AC564 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74AC564 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (each flip-flop)

		INPUTS		OUTPUT
		CLK	D		Q
	OE
	L	↑	H		L
	L	↑	L		H
	L	H or L	X
					Q	0
	H	X	X		Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1996, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN54AC564, SN74AC564

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS551A ± NOVEMBER 1995 ± REVISED MAY 1996

logic symbol²

logic diagram (positive logic)

1	EN
OE				1
11
CLK	C1			OE
2			19	11
				CLK
1D	1D	1	1Q
3			18
2D			2Q		C1
4			17			19	1Q
3D			3Q	2	1D
5			16	1D
4D			4Q
6			15
5D			5Q
7			14
6D			6Q
8			13
7D			7Q		To Seven Other Channels
9			12
8D			8Q

²This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . ±200 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . .	. . . . . . . . . . . . . 0.6 W
DW package . . . . .	. . . . . . . . . . . . . 1.6 W
N package . . . . . . .	. . . . . . . . . . . . . 1.3 W
PW package . . . . .	. . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . ±65°C to 150°C

³ Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2.The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265