Texas Instruments SN65LVDS051DR, SN65LVDS180DR, SN65LVDS050D, SN65LVDS050DR, SN65LVDS051D Datasheet

SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

SLLS301G ± APRIL 1998 ± REVISED MARCH 2000

DMeets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard

DSignaling Rates up to 400 Mbit/s

DBus-Terminal ESD Exceeds 12 kV

DOperates from a Single 3.3-V Supply

DLow-Voltage Differential Signaling With

Typical Output Voltages of 350 mV and a 100 Ω Load

DPropagation Delay Times

±Driver: 1.7 ns Typ

±Receiver: 3.7 ns Typ

DPower Dissipation at 200 MHz

±Driver: 25 mW Typical

±Receiver: 60 mW Typical

DLVTTL Input Levels are 5 V Tolerant

DDriver is High Impedance When Disabled or With VCC < 1.5 V

DReceiver has Open-Circuit Fail Safe

DSurface-Mount Packaging

±D Package (SOIC)

±DGK Package (MSOP) ('LVDS79 Only)

description

The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100 Ω load and receipt of 100 mV signals with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics).

SN65LVDS179D (Marked as DL179 or LVD179) SN65LVDS179DGK (Marked as S79)

(TOP VIEW)

										D		3
VCC						1	8		A
	R					2	7		B			2
	D					3	6		Z	R
GND						4	5		Y
SN65LVDS180D (Marked as LVDS180)
						(TOP VIEW)
NC									VCC
					1		14			D		5
	R
					2		13		VCC			4
	RE				3		12		A	DE		3
	DE				4		11		B
										RE
	D				5		10		Z	R		2
GND					6		9		Y
GND					7		8		NC

SN65LVDS050D (Marked as LVDS050)

(TOP VIEW) 15 1D

	1B				1		16	VCC	12
										DE
	1A				2		15	1D	9
	1R				3		14	1Y		2D
	RE				4		13	1Z	3
	2R				5		12	DE
										1R
	2A				6		11	2Z			4
	2B				7		10	2Y		RE
									5
GND					8		9	2D
										2R
SN65LVDS051D (Marked as LVDS051)
					(TOP VIEW)				15
	1B							VCC		1D
						1	16
									4
	1A					2	15	1D	1DE
	1R							1Y	3
						3	14			1R
1DE						4	13	1Z
	2R					5	12	2DE	9
	2A					6	11	2Z		2D
	2B					7	10	2Y	12
GND						8	9	2D	2DE
									5
										2R

5

Y

6

Z 8

A

7

B

9

Y

10

Z

12

A

11

B

14

1Y

13

1Z

10

2Y

11

2Z

2

1A

1

1B

6

2A

7

2B

14

1Y

13

1Z

2

1A

1

1B

10

2Y

11

2Z

6

2A

7

2B

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2000, Texas Instruments Incorporated

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1

SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051

HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

SLLS301G ± APRIL 1998 ± REVISED MARCH 2000

description (continued)

AVAILABLE OPTIONS

		PACKAGE
TA
	SMALL OUTLINE		SMALL OUTLINE
	(D)		(DGK)
	SN65LVDS050D		Ð
±40°C to 85°C	SN65LVDS051D		Ð
	SN65LVDS179D		SN65LVDS179DGK
	SN65LVDS180D		Ð

NOTE:

The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics.

The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 are characterized for operation from ±40°C to 85°C.

Function Tables

SN65LVDS179 RECEIVER

INPUTS	OUTPUT
VID = VA ± VB	R
VID ≥ 100 mV	H
±100 MV < VID < 100 mV	?
VID ≤ ±100 mV	L
Open	H

H = high level, L = low level, ? = indeterminate

SN65LVDS179 DRIVER

	INPUT		OUTPUTS
	D		Y			Z
	L		L			H
	H		H			L
	Open		L			H
	H = high level,		L = low level
SN65LVDS180, SN65LVDS050, and
	SN65LVDS051 RECEIVER
	INPUTS							OUTPUT
	VID = VA ± VB				RE				R
	VID ≥ 100 mV				L				H
±100 MV < VID < 100 mV					L			?
VID ≤ ±100 mV					L				L
	Open				L				H
	X				H				Z

H = high level, L = low level, Z = high impedance,

X = don't care

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051

HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

SLLS301G ± APRIL 1998 ± REVISED MARCH 2000

SN65LVDS180, SN65LVDS050, and

SN65LVDS051 DRIVER

INPUTS		OUTPUTS
D	DE	Y	Z
L	H	L	H
H	H	H	L
Open	H	L	H
X	L	Z	Z

H = high level, L = low level, Z = high impedance,

X = don't care

equivalent input and output schematic diagrams

			VCC
		VCC
	VCC
	300 kΩ		5 Ω
	50 Ω	10 kΩ
			Y or Z
	D or RE
			Output
	Input
	50	Ω
	DE
	Input		7 V
	7 V
	7 V
	300 kΩ

	VCC		VCC
300 kΩ	300 kΩ
			5 Ω
A Input		B Input	R Output
7 V		7 V	7 V

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3

SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051

HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

SLLS301G ± APRIL 1998 ± REVISED MARCH 2000

absolute maximum ratings over operating free-air temperature (unless otherwise noted)²

Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±0.5 V to 4 V
Voltage range (D, R, DE, RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±0.5 V to 6 V
Electrostatic discharge: Y, Z, A, B , and GND (see Note 2) . . . . . . . . . . . . . . . . . .	CLass 3, A:12 kV, B:600 V
All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. Class 3, A:7 kV, B:500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	see dissipation rating table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . ±65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . 250°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal.

2. Tested in accordance with MIL-STD-883C Method 3015.7.

DISSIPATION RATING TABLE

	PACKAGE	TA ≤ 25°C	DERATING FACTOR	TA = 85°C
		POWER RATING	ABOVE T = 25°C²	POWER RATING
			A
	D8	725 mW	5.8 mW/°C	377 mW
	D14 or D16	950 mW	7.8 mW/°C	494 mW
	DGK	424 mW	3.4 mW/°C	220 mW

² This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

recommended operating conditions

		MIN		NOM	MAX			UNIT
Supply voltage, VCC	3			3.3	3.6			V
High-level input voltage, VIH	2							V
Low-level input voltage, VIL					0.8			V
Magnitude of differential input voltage, VID	0.1				0.6			V
Common±mode input voltage, VIC (see Figure 6)	VID				2.4 *	VID		V
		2				2
					VCC±0.8
Operating free±air temperature, TA	±40				85			°C

device electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN TYP²	MAX	UNIT
	SN65LVDS179	No receiver load, Driver RL = 100 Ω	9	12	mA
		Driver and receiver enabled, No receiver load, Driver RL = 100 Ω	9	12
	SN65LVDS180	Driver enabled, Receiver disabled, RL = 100 Ω	5	7	mA
		Driver disabled, Receiver enabled, No load	1.5	2
Supply		Disabled	0.5	1
		Drivers and receivers enabled, No receiver loads, Driver RL = 100 Ω
ICC current			12	20
	SN65LVDS050	Drivers enabled, Receivers disabled, RL = 100 Ω	10	16	mA
		Drivers disabled, Receivers enabled, No loads	3	6
		Disabled	0.5	1
	SN65LVDS051	Drivers enabled, No receiver loads, Driver RL = 100 Ω	12	20	mA
		Drivers disabled, No loads	3	6

² All typical values are at 25°C and with a 3.3-V supply.

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SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051

HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

SLLS301G ± APRIL 1998 ± REVISED MARCH 2000

driver electrical characteristics over recommended operating conditions (unless otherwise noted)

	PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VOD	Differential output voltage magnitude		RL = 100Ω,	247	340	454
	Change in differential output voltage magnitude between logic						mV
VOD			See Figure 1 and Figure 2	±50		50
	states
VOC(SS)	Steady-state common-mode output voltage			1.125	1.2	1.375	V
VOC(SS)	Change in steady-state common-mode output voltage between		See Figure 3	±50		50	mV
	logic states
VOC(PP)	Peak-to-peak common-mode output voltage				50	150	mV
IIH	High-level input current	DE	VIH = 5 V		± 0.5	± 20	µA
		D			2	20
IIL	Low-level input current	DE	VIL = 0.8 V		± 0.5	±10	µA
		D			2	10
IOS	Short-circuit output current		VOY or VOZ = 0 V		3	10	mA
			VOD = 0 V		3	10
IOZ	High-impedance output current		VOD = 600 mV			±1	µA
			VO = 0 V or VCC			±1
IO(OFF)	Power-off output current		VCC = 0 V, VO = 3.6 V			±1	µA
CIN	Input capacitance				3		pF

receiver electrical characteristics over recommended operating conditions (unless otherwise noted)

	PARAMETER	TEST CONDITIONS	MIN	TYP²	MAX	UNIT
VITH+	Positive-going differential input voltage threshold	See Figure 5 and Table 1			100	mV
VITH±	Negative-going differential input voltage threshold		±100
VOH	High-level output voltage	IOH = ±8 mA	2.4			V
VOL	Low-level output voltage	IOL = 8 mA			0.4	V
II	Input current (A or B inputs)	VI = 0	±2	±11	±20	µA
		VI = 2.4 V	±1.2	±3
II(OFF)	Power-off input current (A or B inputs)	VCC = 0			±20	µA
IIH	High-level input current (enables)	VIH = 5 V			±10	µA
IIL	Low-level input current (enables)	VIL = 0.8 V			±10	µA
IOZ	High-impedance output current	VO = 0 or 5 V			±10	µA
CI	Input capacitance			5		pF

² All typical values are at 25°C and with a 3.3-V supply.

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5

SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051

HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

SLLS301G ± APRIL 1998 ± REVISED MARCH 2000

driver switching characteristics over recommended operating conditions (unless otherwise noted)

				PARAMETER		TEST CONDITIONS	MIN TYP²	MAX	UNIT
	tPLH	Propagation delay time, low-to-high-level output					1.7	2.7	ns
	tPHL	Propagation delay time, high-to-low-level output				RL = 100Ω,	1.7	2.7	ns
	t	Differential output signal rise time					0.8	1	ns
	r					CL = 10 pF,
	tf	Differential output signal fall time					0.8	1	ns
						See Figure 6
	t	Pulse skew (|t	pHL	± t	|)³		300		ps
	sk(p)			pLH
	t	Channel-to-channel output skew§					150		ps
	sk(o)
	tPZH	Propagation delay time, high-impedance-to-high-level output					4.3	10	ns
	tPZL	Propagation delay time, high-impedance-to-low-level output				See Figure 7	4.6	10	ns
	tPHZ	Propagation delay time, high-level-to-high-impedance output					3.1	10	ns
	tpLZ	Propagation delay time, low-level-to-high-impedance output					3.4	10	ns
	² All typical values are at 25°C and with a 3.3-V.
	³ t	is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
	sk(p)
	§ t	is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
	sk(o)

¶tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, same temperature, and have identical packages and test circuits.

receiver switching characteristics over recommended operating conditions (unless otherwise noted)

			PARAMETER		TEST CONDITIONS			MIN TYP²	MAX	UNIT
tPLH	Propagation delay time, low-to-high-level output							3.7	4.5	ns
tPHL	Propagation delay time, high-to-low-level output							3.7	4.5	ns
t	Pulse skew (|t	pHL	± t	|)³	C	L	= 10 pF, See Figure 6	0.3		ns
sk(p)			pLH
tr	Output signal rise time							0.7	1.5	ns
tf	Output signal fall time							0.9	1.5	ns
tPZH	Propagation delay time, high-level-to-high-impedance output							2.5		ns
tPZL	Propagation delay time, low-level-to-low-impedance output				See Figure 7			2.5		ns
tPHZ	Propagation delay time, high-impedance-to-high-level output							7		ns
tPLZ	Propagation delay time, low-impedance-to-high-level output							4		ns
² All typical values are at 25°C and with a 3.3-V.
³ t	is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
sk(p)
§ t	is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
sk(o)

¶tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, same temperature, and have identical packages and test circuits.

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