Texas Instruments SN74ABT651DBLE, SN74ABT651DBR, SN74ABT651DW, SN74ABT651DWR, SN74ABT651NT Datasheet

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SN54ABT651, SN74ABT651

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

					SCBS083E ± JANUARY 1991 ± REVISED APRIL 1998

D	State-of-the-Art EPIC-	ΙΙ	B	BiCMOS Design	SN54ABT651 . . . JT PACKAGE
	State-of-the-Art EPIC-		B	BiCMOS Design	SN74ABT651 . . . DB, DW, NT, OR PW PACKAGE
	Significantly Reduces Power Dissipation				SN74ABT651 . . . DB, DW, NT, OR PW PACKAGE
					(TOP VIEW)

DESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

CLKAB

VCC

Using Machine Model (C = 200 pF, R = 0)

SAB

CLKBA

D Latch-Up Performance Exceeds 500 mA Per

OEAB

SBA

JESD 17

OEBA

D Typical VOLP (Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25 C

D High-Drive Outputs (±32-mA IOH,

64-mA IOL )

D Multiplexed Real-Time and Stored Data

Inverting Data Paths

D Package Options Include Plastic

GND

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

SN54ABT651 . . . FK PACKAGE

Packages, Ceramic Chip Carriers (FK), and

(TOP VIEW)

Plastic (NT) and Ceramic (JT) DIPs

OEAB

SAB

CLKAB

CLKBA

SAB

description

These devices consist of bus-transceiver circuits,

27 26

D-type flip-flops, and control circuitry arranged for

OEBA

multiplexed transmission of data directly from the

data bus or from the internal storage registers.

Output-enable (OEAB

and

OEBA) inputs are

provided to control the transceiver functions. The

select-control (SAB and SBA) inputs are provided

to select

whether real-time

or stored data is

transferred. A low input level selects real-time

12 13 14 15 16 17 18

data, and a high input level selects stored data.

GND

Figure

illustrates

the

four

fundamental

bus-management functions that can be

performed with the 'ABT651 devices.

NC ± No internal connection

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the selector enable-control pins. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all the other data sources to the two sets of bus lines are at high impedance, each set remains at its last state.

To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver (B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver (A to B).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABT651, SN74ABT651

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS083E ± JANUARY 1991 ± REVISED APRIL 1998

description (continued)

The SN54ABT651 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT651 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE

INPUTS

DATA I/O

OPERATION OR FUNCTION

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

A1±A8

B1±B8

H or L

Input

Isolation

↑

Input

Store A and B data

↑

H or L

Input

Unspecified²

Store A, hold B

↑

X³

Input

Output

Store A in both registers

H or L

↑

Unspecified²

Input

Hold A, store B

↑

X³

Output

Input

Store B in both registers

Output

Input

Real-time

data to A bus

H or L

Output

Input

Stored

data to A bus

Input

Output

Real-time

data to B bus

H or L

Input

Output

Stored

data to B bus

H or L

Output

Stored

data to B bus and

stored B data to A bus

²The data output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

³When select control is low, clocks can occur simultaneously if allowances are made for propagation delays from A to B (B to A) plus setup and hold times. When select control is high, clocks must be staggered to load both registers.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Texas Instruments SN74ABT651DBLE, SN74ABT651DBR, SN74ABT651DW, SN74ABT651DWR, SN74ABT651NT Datasheet

SN54ABT651, SN74ABT651

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS083E ± JANUARY 1991 ± REVISED APRIL 1998

BUS A

BUS B

BUS A

BUS B

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

REAL-TIME TRANSFER

BUS B TO BUS A

BUS A TO BUS B

BUS A

BUS B

BUS A

BUS B

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

↑

H or L

↑

TRANSFER STORED DATA TO A AND/OR B

↑

STORAGE FROM A, B, OR A AND B

Pin numbers are for the DB, DW, JT, NT, and PW packages.

Figure 1. Bus-Management Functions

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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