Texas Instruments SN74ACT3622-30PCB, SN74ACT3622-30PQ, SN74ACT3622-15PCB, SN74ACT3622-15PQ, SN74ACT3622-20PCB Datasheet

																																																																										SN74ACT3622
																																																																												256 ×36	×2
																					CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
																																																								SCAS247D ± AUGUST 1993 ± REVISED APRIL 1998
D Free-Running CLKA and CLKB Can Be																																								D IRB, ORB,																							and										Flags
																																																									AEB,											AFB
Asynchronous or Coincident																																												Synchronized by CLKB
D Two Independent Clocked FIFOs Buffering																																								D Low-Power 0.8 μm Advanced CMOS
Data in Opposite Directions																																												Technology
D Mailbox-Bypass Register for Each FIFO																																								D Supports Clock Frequencies up to 67 MHz
D Programmable Almost-Full and																																								D Fast Access Times of 11 ns
Almost-Empty Flags																																								D Pin-to-Pin Compatible With the
D Microprocessor Interface Control Logic																																												SN74ACT3632 and SN74ACT3642
D IRA, ORA,				and								Flags																												D Package Options Include 120-Pin Thin
	AEA,							AFA
Synchronized by CLKA																																												Quad Flat (PCB) and 132-Pin Plastic Quad
																																												Flat (PQ) Packages
																														PCB PACKAGE
																															(TOP VIEW)
			GND CLKA					W/RA																	MBF2					RST1					GND FS1					RST2				MBF1															GND				CSB W/RB						CLKB
						ENA					CSA		IRA			ORA		V			AFA		AEA			MBA						FS0										MBB				V			AEB		AFB ORB						IRB										ENB					V
																			CC																												CC																									CC
A35		120		119		118		117			116		115			114		113			112		111		110	109			108		107			106		105			104			103		102		101			100		99		98			97			96				95		94		93		92			91				B35
		1																																																																						90
A34		2																																																																						89				B34
A33		3																																																																						88				B33
A32		4																																																																						87				B32
VCC		5																																																																						86				GND
A31		6																																																																						85				B31
A30		7																																																																						84				B30
GND		8																																																																						83				B29
A29		9																																																																						82				B28
A28		10																																																																						81				B27
A27		11																																																																						80				B26
A26		12																																																																						79				VCC
A25		13																																																																						78				B25
A24		14																																																																						77				B24
A23		15																																																																						76				GND
GND		16																																																																						75				B23
A22		17																																																																						74				B22
VCC		18																																																																						73				B21
A21		19																																																																						72				B20
A20		20																																																																						71				B19
A19		21																																																																						70				B18
A18		22																																																																						69				GND
GND		23																																																																						68				B17
A17		24																																																																						67				B16
A16		25																																																																						66				VCC
A15		26																																																																						65				B15
A14		27																																																																						64				B14
A13		28																																																																						63				B13
VCC		29																																																																						62				B12
A12		30																																																																						61				GND
		31		32		33		34			35		36			37		38			39		40		41	42			43		44			45		46			47			48		49		50			51		52		53			54			55				56		57		58		59			60
			GND A11 A10					A9			A8		A7			A6			GND		A5		A4 A3			V				A2	A1			A0		GND				B0		B1		B2			B3		B4		B5		GND										B7		B8 B9							B11
																																																								B6 V														B10
																											CC																																	CC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1998, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN74ACT3622 256 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS247D ± AUGUST 1993 ± REVISED APRIL 1998

PQ PACKAGE² (TOP VIEW)

				NC			NC		V			CLKB		ENB W/RB				CSB		GND			IRB		ORB			AFB		AEB			V			MBF1			MBB		RST2			FS1			GND		FS0		RST1		MBA			MBF2		AEA				AFA			V				ORA		IRA				CSA		W/RA		ENA			CLKA			GND			NC
										CC																								CC																																CC
	17 16 15 14 13 12 11 10																					9			8			7		6			5			4		3			2			1 132					130						128						126							124						122					120						118
NC			18																																												131				129							127							125						123						121					119						117
																																																																																								116
B35			19																																																																																					115
B34			20																																																																																					114
B33			21																																																																																					113
B32			22																																																																																					112
GND			23																																																																																					111
B31			24																																																																																					110
B30			25																																																																																					109
B29			26																																																																																					108
B28			27																																																																																					107
B27			28																																																																																					106
B26			29																																																																																					105
VCC			30																																																																																					104
B25			31																																																																																					103
B24			32																																																																																					102
GND			33																																																																																					101
B23			34																																																																																					100
B22			35																																																																																					99
B21			36																																																																																					98
B20			37																																																																																					97
B19			38																																																																																					96
B18			39																																																																																					95
GND			40																																																																																					94
B17			41																																																																																					93
B16			42																																																																																					92
VCC			43																																																																																					91
B15			44																																																																																					90
B14			45																																																																																					89
B13			46																																																																																					88
B12			47																																																																																					87
GND			48																																																																																					86
NC			49																																																																																					85
NC			50																																																																																					84
			51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
				NC			B11		B10			B9		B8 B7				V		B6		GND			B5			B4		B3			B2			B1		B0			GND			A0			A1		A2		V		A3			A4		A5				GND			A6			A7				A8			A9		A10		A11			GND			NC			NC
																		CC																																	CC

NC ± No internal connection

² Uses Yamaichi socket IC51-1324-828

NC

NC

A35

A34

A33

A32

VCC

A31

A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22

VCC

A21

A20

A19

A18 GND A17 A16 A15 A14 A13

VCC

A12

NC

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ACT3622 256 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS247D ± AUGUST 1993 ± REVISED APRIL 1998

description

The SN74ACT3622 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock frequencies up to 67 MHz with read access times of 11 ns. Two independent 256 ×36 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags almost full (AF) and almost empty (AE) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths.

The SN74ACT3622 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The input-ready (IRA, IRB) flag and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA, AEB) flag of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the AF and AE flags of the FIFO can be programmed from port A.

The SN74ACT3622 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the application report FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) and Metastability Performance of Clocked FIFOs (literature number SCZA004).

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

SN74ACT3622 256 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS247D ± AUGUST 1993 ± REVISED APRIL 1998

functional block diagram

				Mail1
CLKA				Register
CSA	Port-A
W/RA	Control		RegisterInput			RegisterOutput
ENA	Mail1
	Logic
MBA				256 × 36
				SRAM
	FIFO1,
RST1	Reset
	Logic
				Write	Read
				Pointer	Pointer
IRA				Status-Flag
AFA			FIFO1	Logic
		36
FS0				Programmable-
				Flag
FS1
			10	Offset Registers
A0 ± A35
			FIFO2	Status-Flag
ORA
AEA				Logic
				Read	Write
			RegisterOutput	Pointer	Pointer
				256 × 36		RegisterInput
				SRAM
				Mail2
				Register
MBF2

MBF1

36

ORB

AEB

B0 ± B35

IRB

AFB

36

FIFO2,

Mail2

Reset RST2

Logic

CLKB

Port-B CSB

Control W/RB

Logic

ENB

MBB

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ACT3622

256 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS247D ± AUGUST 1993 ± REVISED APRIL 1998

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

A0 ± A35

I/O

Port-A data. The 36-bit bidirectional data port for side A.

O

Port-A almost-empty flag. Programmable flag synchronized to CLKA.

AEA

is low when the number of words in FIFO2

AEA

(port A)

is less than or equal to the value in the almost-empty A offset register, X2.

O

Port-B almost-empty flag. Programmable flag synchronized to CLKB.

is low when the number of words in FIFO1

AEB

AEB

(port B)

is less than or equal to the value in the almost-empty B offset register, X1.

O

Port-A almost-full flag. Programmable flag synchronized to CLKA.

is low when the number of empty locations in

AFA

AFA

(port A)

FIFO1 is less than or equal to the value in the almost-full A offset register, Y1.

O

Port-B almost-full flag. Programmable flag synchronized to CLKB.

is low when the number of empty locations in

AFB

AFB

(port B)

FIFO2 is less than or equal to the value in the almost-full B offset register, Y2.

B0 ± B35

I/O

Port-B data. The 36-bit bidirectional data port for side B.

CLKA

I

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous

or coincident to CLKB. IRA, ORA, AFA, and AEA are all synchronized to the low-to-high transition of CLKA.

CLKB

I

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous

or coincident to CLKA. IRB, ORB, AFB, and AEB are synchronized to the low-to-high transition of CLKB.

Port-A chip select.

must be low to enable a low-to-high transition of CLKA to read or write data on port A. The

I

CSA

CSA

A0 ± A35 outputs are in the high-impedance state when CSA is high.

I

Port-B chip select.

CSB

must be low to enable a low-to-high transition of CLKB to read or write data on port B. The

CSB

B0 ± B35 outputs are in the high-impedance state when CSB is high.

ENA

I

Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.

ENB

I

Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.

Flag offset selects. The low-to-high transition of a FIFO's reset input latches the values of FS0 and FS1. If either FS0

FS1, FS0

I

or FS1 is high when a reset input goes high, one of three preset values is selected as the offset for the FIFO AF and

AE flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are low when RST1 and RST2 go high, the

first four writes to FIFO1 program the almost-full and almost-empty offsets for both FIFOs.

O

Input-ready flag. IRA is synchronized to the low-to-high transition of CLKA. When IRA is low, FIFO1 is full and writes

IRA

to its array are disabled. IRA is set low when FIFO1 is reset and is set high on the second low-to-high transition of CLKA

(port A)

after reset.

O

Input-ready flag. IRB is synchronized to the low-to-high transition of CLKB. When IRB is low, FIFO2 is full and writes

IRB

to its array are disabled. IRB is set low when FIFO2 is reset and is set high on the second low-to-high transition of CLKB

(port B)

after reset.

Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the

MBA

I

A0 ± A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects

FIFO2 output-register data for output.

Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the

MBB

I

B0 ± B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects

FIFO1 output-register data for output.

Mail1 register flag.

is set low by a low-to-high transition of CLKA that writes data to the mail1 register. Writes to

MBF1

MBF1

O

the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B

read is selected and MBB is high. MBF1 is set high when FIFO1 is reset.

Mail2 register flag.

is set low by a low-to-high transition of CLKB that writes data to the mail2 register. Writes to

MBF2

MBF2

O

the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A

read is selected and MBA is high. MBF2 is also set high when FIFO2 is reset.

Output-ready flag. ORA is synchronized to the low-to-high transition of CLKA. When ORA is low, FIFO2 is empty and

ORA

O

reads from its memory are disabled. Ready data is present on the output register of FIFO2 when ORA is high. ORA

(port A)

is forced low when FIFO2 is reset and goes high on the third low-to-high transition of CLKA after a word is loaded to

empty memory.

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5

SN74ACT3622 256 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS247D ± AUGUST 1993 ± REVISED APRIL 1998

Terminal Functions (continued)

TERMINAL

I/O

DESCRIPTION

NAME

Output-ready flag. ORB is synchronized to the low-to-high transition of CLKB. When ORB is low, FIFO1 is empty and

ORB

O

reads from its memory are disabled. Ready data is present on the output register of FIFO1 when ORB is high. ORB

(port B)

is forced low when FIFO1 is reset and goes high on the third low-to-high transition of CLKB after a word is loaded to

empty memory.

FIFO1 reset. To reset FIFO1, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur

RST1

I

while

RST1

is low. The low-to-high transition of RST1 latches the status of FS0 and FS1 for

AFA

and AEB offset

selection. FIFO1 must be reset upon power up before data is written to its RAM.

FIFO2 reset. To reset FIFO2, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur

RST2

I

while

RST2

is low. The low-to-high transition of RST2 latches the status of FS0 and FS1 for

AFB

and AEA offset

selection. FIFO2 must be reset upon power up before data is written to its RAM.

I

Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a

W/RA

low-to-high transition of CLKA. The A0 ± A35 outputs are in the high-impedance state when W/RA is high.

I

Port-B write/read select. A low on

W/RB selects a write operation and a high selects a read operation on port B for a

W/RB

low-to-high transition of CLKB. The B0 ± B35 outputs are in the high-impedance state when W/RB is low.

detailed description

reset

The FIFO memories of the SN74ACT3622 are reset separately by taking their reset (RST1, RST2) inputs low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset inputs can switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the input-ready (IRA, IRB) flag low, the output-ready (ORA, ORB) flag low, the almost-empty (AEA, AEB) flag low, and the almost-full (AFA, AFB) flag high. Resetting a FIFO also forces the mailbox (MBF1, MBF2) flag of the parallel mailbox register high. After a FIFO is reset, its IR flag is set high after two clock cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory.

A low-to-high transition on a FIFO reset (RST1, RST2) input latches the value of the flag-select (FS0, FS1) inputs for choosing the almost-full and almost-empty offset programming method (see almost-empty flag and almost-full flag offset programming).

almost-empty flag and almost-full flag offset programming

Four registers in the SN74ACT3622 are used to hold the offset values for the AE and AF flags. The port-B almost-empty (AEB) flag offset register is labeled X1 and the port-A almost-empty (AEA) flag offset register is labeled X2. The port-A almost-full (AFA) flag offset register is labeled Y1 and the port-B almost-full (AFB) flag offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from port A (see Table 1).

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ACT3622 256 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS247D ± AUGUST 1993 ± REVISED APRIL 1998

almost-empty flag and almost-full flag offset programming (continued)

Table 1. Flag Programming

FS1	FS0							X1 AND Y1 REGISTERS²	X2 AND Y2 REGISTERS³
			RST1			RST2
H	H		↑			X		64	X
H	H		X			↑		X	64
H	L		↑			X		16	X
H	L		X			↑		X	16
L	H		↑			X		8	X
L	H		X			↑		X	8
L	L		↑			↑		Programmed from port A	Programmed from port A

² X1 register holds the offset for AEB; Y1 register holds the offset for AFA. ³ X2 register holds the offset for AEA; Y2 register holds the offset for AFB.

To load the FIFO AE flag and AF flag offset registers with one of the three preset values listed in Table 1, at least one of the flag-select inputs must be high during the low-to-high transition of its reset input. For example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be high when FIFO1 reset (RST1) returns high. Flag-offset registers associated with FIFO2 are loaded with one of the preset values in the same way with FIFO2 reset (RST2). When using one of the preset values for the flag offsets, the FIFOs can be reset simultaneously or at different times.

To program the X1, X2, Y1, and Y2 registers from port A, both FIFOs should be reset simultaneously with FS0 and FS1 low during the low-to-high transition of the reset inputs. After this reset is complete, the first four writes to FIFO1 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. Each offset register uses port-A inputs (A7±A0). The highest numbered input is used as the most-significant bit of the binary number in each case. Valid programming values for the registers range from 1 to 252. After all the offset registers are programmed from port A, the port-B input-ready (IRB) flag is set high and both FIFOs begin normal operation.

FIFO write/read operation

The state of the port-A data (A0±A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0±A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0±A35 outputs are active when both CSA and W/RA are low.

Data is loaded into FIFO1 from the A0±A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low, and IRA is high. Data is read from FIFO2 to the A0±A35 outputs by a low-to-high transition of CLKA when CSA is low, W/RA is low, ENA is high, MBA is low, and ORA is high (see Table 2). FIFO reads and writes on port A are independent of any concurrent port-B operation.

Table 2. Port-A Enable Function Table

CSA

W/RA

ENA

MBA

CLKA

A0 ± A35 OUTPUTS

PORT FUNCTION

H

X

X

X

X

In high-impedance state

None

L

H

L

X

X

In high-impedance state

None

L

H

H

L

↑

In high-impedance state

FIFO1 write

L

H

H

H

↑

In high-impedance state

Mail1 write

L

L

L

L

X

Active, FIFO2 output register

None

L

L

H

L

↑

Active, FIFO2 output register

FIFO2 read

L

L

L

H

X

Active, mail2 register

None

↑

L

L

H

H

Active, mail2 register

Mail2 read (set

MBF2

high)

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7

SN74ACT3622 256 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS247D ± AUGUST 1993 ± REVISED APRIL 1998

FIFO write/read operation (continued)

The port-B control signals are identical to those of port A, with the exception that the port-B write/read select (W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0±B35) outputs is controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0±B35 outputs are in the high-impedance state when either CSB is high or W/RB is low. The B0±B35 outputs are active when CSB is low and W/RB is high.

Data is loaded into FIFO2 from the B0±B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB is low, ENB is high, MBB is low, and IRB is high. Data is read from FIFO1 to the B0±B35 outputs by a low-to-high transition of CLKB when CSB is low, W/RB is high, ENB is high, MBB is low, and ORB is high (see Table 3). FIFO reads and writes on port B are independent of any concurrent port-A operation.

Table 3. Port-B Enable Function Table

CSB

W/RB

ENB

MBB

CLKB

B0 ± B35 OUTPUTS

PORT FUNCTION

H

X

X

X

X

In high-impedance state

None

L

L

L

X

X

In high-impedance state

None

L

L

H

L

↑

In high-impedance state

FIFO2 write

L

L

H

H

↑

In high-impedance state

Mail2 write

L

H

L

L

X

Active, FIFO1 output register

None

L

H

H

L

↑

Active, FIFO1 output register

FIFO1 read

L

H

L

H

X

Active, mail1 register

None

↑

L

H

H

H

Active, mail1 register

Mail1 read (set

MBF1

high)

The setupand hold-time constraints to the port clocks for the port-chip selects and write/read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select may change states during the setupand hold-time window of the cycle.

When a FIFO OR flag is low, the next data word is sent to the FIFO output register automatically by the low-to-high transition of the port clock that sets the OR flag high. When the OR flag is high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the port's chip select, write/read select, enable, and mailbox select.

synchronized FIFO flags

Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asynchronously to one another. ORA, AEA, IRA, and AFA are synchronized to CLKA. ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2.

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ACT3622 256 ×36 ×2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS247D ± AUGUST 1993 ± REVISED APRIL 1998

synchronized FIFO flags (continued)

Table 4. FIFO1 Flag Operation

NUMBER OF WORDS IN	SYNCHRONIZED			SYNCHRONIZED
	TO CLKB				TO CLKA
FIFO1²³
	ORB					IRA
		AEB		AFA
0	L	L			H	H
1 to X1	H	L			H	H
(X1 + 1) to [256 ± (Y1 + 1)]	H	H			H	H
(256 ± Y1) to 255	H	H			L	H
256	H	H			L	L

²X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset

of FIFO1 or programmed from port A.

³When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

Table 5. FIFO2 Flag Operation

	NUMBER OF WORDS IN	SYNCHRONIZED			SYNCHRONIZED
		TO CLKA				TO CLKB
	FIFO2²³
		ORA	AEA		AFB		IRB
	0	L	L			H	H
	1 to X2	H	L			H	H
	(X2 + 1) to [256 ± (Y2 + 1)]	H	H			H	H
	(256 ± Y2) to 255	H	H			L	H
	256	H	H			L	L

² X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or programmed from port A.

³When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

output-ready flags (ORA, ORB)

The OR flag of a FIFO is synchronized to the port clock that reads data from its array. When the OR flag is high, new data is present in the FIFO output register. When the OR flag is low, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored.

A FIFO read pointer is incremented each time a new word is clocked to its output register. From the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the OR flag synchronizing clock; therefore, an OR flag is low if a word in memory is the next data to be sent to the FIFO output register and three cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The OR flag of the FIFO remains low until the third low-to-high transition of the synchronizing clock occurs, simultaneously forcing the OR flag high and shifting the word to the FIFO output register.

A low-to-high transition on an OR flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 7 and 8).

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