Texas Instruments SN74ABT533ADBLE, SN74ABT533ADBR, SN74ABT533ADW, SN74ABT533ADWR, SN74ABT533AN Datasheet

	SN54ABT533, SN74ABT533A
	OCTAL TRANSPARENT D-TYPE LATCHES
	WITH 3-STATE OUTPUTS
	SCBS186D ± JANUARY 1991 ± REVISED JANUARY 1997
D State-of-the-Art EPIC-ΙΙB BiCMOS Design	SN54ABT533 . . . J OR W PACKAGE
Significantly Reduces Power Dissipation	SN74ABT533A . . . DB, DW, N, OR PW PACKAGE
	(TOP VIEW)

DLatch-Up Performance Exceeds 500 mA Per

	JEDEC Standard JESD-17
		OE				1	20	VCC
	D Typical VOLP (Output Ground Bounce) < 1 V
			1Q			2	19	8Q
	at VCC = 5 V, TA = 25°C		1D			3	18	8D
	D High-Drive Outputs (±32-mA IOH, 64-mA IOL)		2D			4	17	7D
	D ESD Protection Exceeds 2000 V Per		2Q			5	16	7Q
	MIL-STD-883, Method 3015; Exceeds 200 V		3Q			6	15	6Q
	Using Machine Model (C = 200 pF, R = 0)		3D			7	14	6D
	D Package Options Include Plastic		4D			8	13	5D
			4Q			9	12	5Q
	Small-Outline (DW), Shrink Small-Outline
		GND				10	11	LE
	(DB), and Thin Shrink Small-Outline (PW)
	Packages, Ceramic Chip Carriers (FK),	SN54ABT533 . . . FK PACKAGE
	Plastic (N) and Ceramic (J) DIPs, and
	Ceramic Flat (W) Package					(TOP VIEW)

description

These octal transparent D-type latches with 3-state outputs are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

When the latch-enable (LE) input is high, the Q outputs follow the complements of the data

(D) inputs. When LE is taken low, the Q outputs are latched at the inverse of the levels at the D inputs.

	1D	1Q	OE	CC	8Q
				V
2D	3	2	1	20 19		8D
	4				18
2Q	5				17	7D
3Q	6				16	7Q
3D	7				15	6Q
4D	8	10 11			14	6D
	9			12 13
	4Q	GND	LE	5Q	5D

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect the internal operations of the latches. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT533 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT533A is characterized for operation from ±40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN54ABT533, SN74ABT533A

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS186D ± JANUARY 1991 ± REVISED JANUARY 1997

			FUNCTION TABLE
			(each latch)
			INPUTS		OUTPUT
			LE	D		Q
		OE
		L	H	H		L
		L	H	L		H
		L	L	X
						Q	0
		H	X	X		Z
logic symbol²				logic diagram (positive logic)

1					OE	1
	EN
OE
11					LE	11
LE	C1
						C1	2
3			2				1Q
						3
1D	1D	1		1Q	1D
						1D
4			5
				2Q
2D
7			6
3D			9	3Q
8
4D			12	4Q		To Seven Other Channels
13
5D			15	5Q
14				6Q
6D			16
17
7D			19	7Q
18
8D				8Q

²This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . . ±0.5 V to 5.5 V

Current into any output in the low state, IO: SN54ABT533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT533A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W

N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±65°C to 150°C

³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2.The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABT533, SN74ABT533A

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS186D ± JANUARY 1991 ± REVISED JANUARY 1997

recommended operating conditions (see Note 3)

		SN54ABT533		SN74ABT533A		UNIT
		MIN	MAX	MIN	MAX
VCC	Supply voltage	4.5	5.5	4.5	5.5	V
VIH	High-level input voltage	2		2		V
VIL	Low-level input voltage		0.8		0.8	V
VI	Input voltage	0	VCC	0	VCC	V
IOH	High-level output current		±24		±32	mA
IOL	Low-level output current		48		64	mA
t/ v	Input transition rise or fall rate		10		10	ns/V
TA	Operating free-air temperature	±55	125	±40	85	°C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25°C

SN54ABT533

SN74ABT533A

UNIT

MIN

TYP²

MAX

MIN

MAX

MIN

MAX

VIK

VCC = 4.5 V,

II = ±18 mA

±1.2

±1.2

±1.2

V

VCC = 4.5 V,

IOH = ±3 mA

2.5

2.5

2.5

VOH

VCC = 5 V,

IOH = ±3 mA

3

3

3

V

VCC = 4.5 V

IOH = ±24 mA

2

2

IOH = ±32 mA

2*

2

VOL

VCC = 4.5 V

IOL = 48 mA

0.55

0.55

V

IOL = 64 mA

0.55*

0.55

Vhys

100

mV

II

VCC = 5.5 V,

VI = VCC or GND

±1

±1

±1

µA

IOZH

VCC = 5.5 V,

VO = 2.7 V

10

10

10

µA

IOZL

VCC = 5.5 V,

VO = 0.5 V

±10

±10

±10

µA

Ioff

VCC = 0,

VI or VO ≤ 4.5 V

±150

±150

µA

ICEX

VCC = 5.5 V,

VO = 5.5 V

Outputs high

50

50

50

µA

I ³

V = 5.5 V,

V = 2.5 V

±50

±140

±180

±50

±180

±50

±180

mA

O

CC

O

VCC = 5.5 V, IO

= 0,

Outputs high

1

250

250

250

µA

ICC

Outputs low

24

30

30

30

mA

VI = VCC or GND

Outputs disabled

0.5

250

250

250

µA

VCC = 5.5 V,

Outputs high

1.5

1.5

1.5

ICC§

mA

Outputs low

1.5

1.5

1.5

One input at 3.4 V,

Other inputs at VCC or GND

Outputs disabled

1.5

1.5

1.5

Ci

VI = 2.5 V or 0.5 V

3.5

pF

Co

VO = 2.5 V or 0.5 V

6.5

pF

* On products compliant to MIL-PRF-38535, this parameter does not apply.

² All typical values are at VCC = 5 V.

³ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than V

CC

or GND.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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