Texas Instruments SN74ABT377ADBLE, SN74ABT377ADBR, SN74ABT377ADW, SN74ABT377ADWR, SN74ABT377AN Datasheet

	SN54ABT377, SN74ABT377A
	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
	WITH CLOCK ENABLE
	SCBS156E ± FEBRUARY 1991 ± REVISED JANUARY 1997
D State-of-the-Art EPIC-ΙΙB BiCMOS Design	SN54ABT377 . . . J OR W PACKAGE
Significantly Reduces Power Dissipation	SN74ABT377A . . . DB, DW, N, OR PW PACKAGE
	(TOP VIEW)

DLatch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17									VCC
	CLKEN					1	20
D Typical VOLP (Output Ground Bounce) < 1 V	1Q					2	19		8Q
at VCC = 5 V, TA = 25°C	1D					3	18		8D
D High-Drive Outputs (±32-mA IOH, 64-mA IOL)	2D					4	17		7D
D ESD Protection Exceeds 2000 V Per	2Q		5				16		7Q
MIL-STD-883, Method 3015; Exceeds 200 V	3Q					6	15		6Q
Using Machine Model (C = 200 pF, R = 0)	3D					7	14		6D
D Package Options Include Plastic	4D					8	13		5D
	4Q		9				12		5Q
Small-Outline (DW), Shrink Small-Outline
	GND						11		CLK
			10
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and	SN54ABT377 . . . FK PACKAGE
Ceramic Flat (W) Package			(TOP VIEW)

description

These 8-bit positive-edge-triggered D-type flip-flops with a clock (CLK) input are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators.

Data (D) input information that meets the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the common clock-enable (CLKEN) input is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the buffered clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at CLKEN.

	1D	1Q	CLKEN	CC	8Q
				V
2D	3	2	1	20 19		8D
	4				18
2Q	5				17	7D
3Q	6				16	7Q
3D	7				15	6Q
4D	8				14	6D
	9	10 11 12 13
	4Q	GND	CLK	5Q	5D

The SN54ABT377 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT377A is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (each flip-flop)

			INPUTS		OUTPUT
			CLK	D	Q
	CLKEN
	H		X	X	Q0
	L		↑	H	H
	L		↑	L	L
	X		H or L	X	Q0

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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SN54ABT377, SN74ABT377A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLOCK ENABLE

SCBS156E ± FEBRUARY 1991 ± REVISED JANUARY 1997

logic symbol²

	1		G1
CLKEN
11				1C2
CLK
3						2
1D			2D				1Q
4						5
2D							2Q
7						6
3D							3Q
8						9
4D							4Q
13						12
5D							5Q
14						15
6D							6Q
17						16
7D							7Q
18						19
8D							8Q

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

11

CLK

1

CLKEN

3

1D

1D	2
	1Q
C1

To Seven Other Channels

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ABT377, SN74ABT377A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLOCK ENABLE

SCBS156E ± FEBRUARY 1991 ± REVISED JANUARY 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . .	±0.5 V to 5.5	V
Current into any output in the low state, IO: SN54ABT377 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 96 mA
SN74ABT377A . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 115°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 128°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±65°C to 150°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2.The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.

recommended operating conditions (see Note 3)

			SN54ABT377		SN74ABT377A		UNIT
			MIN	MAX	MIN	MAX
VCC	Supply voltage		4.5	5.5	4.5	5.5	V
VIH	High-level input voltage		2		2		V
VIL	Low-level input voltage			0.8		0.8	V
VI	Input voltage		0	VCC	0	VCC	V
IOH	High-level output current			±24		±32	mA
IOL	Low-level output current			48		64	mA
t/ v	Input transition rise or fall rate	Outputs enabled		5		5	ns/V
TA	Operating free-air temperature		±55	125	±40	85	°C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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