Texas Instruments SN74ACT373DBLE, SN74ACT373DBR, SN74ACT373DW, SN74ACT373DWR, SN74ACT373N Datasheet

SN54ACT373, SN74ACT373

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS544D ± OCTOBER 1995 ± REVISED JANUARY 2000

D Inputs Are TTL-Voltage Compatible

SN54ACT373 . . . J OR W PACKAGE

D

EPIC (Enhanced-Performance Implanted

SN74ACT373 . . . DB, DW, N, OR PW PACKAGE

(TOP VIEW)

CMOS) 1- m Process

D Package Options Include Plastic

OE

1

20

VCC

Small-Outline (DW) Shrink Small-Outline

1Q

2

19

8Q

(DB), and Thin Shrink Small-Outline (PW)

1D

3

18

8D

Packages, Ceramic Chip Carriers (FK) and

2D

4

17

7D

Flatpacks (W), and Standard Plastic (N) and

2Q

5

16

7Q

Ceramic (J) DIPs

3Q

6

15

6Q

description

3D

7

14

6D

4D

8

13

5D

These 8-bit latches feature 3-state outputs

4Q

9

12

5Q

designed specifically for driving highly capacitive

GND

10

11

LE

or relatively low-impedance loads. The devices

are particularly suitable for implementing buffer

SN54ACT373 . . . FK PACKAGE

registers, I/O ports, bidirectional bus drivers, and

(TOP VIEW)

working registers.

1D 1Q

CC

8Q

The eight latches are D-type transparent latches.

OE V

When the latch-enable (LE) input is high, the Q

2D

3

2

1 20 19

8D

outputs follow the data (D) inputs. When LE is

4

18

taken low, the Q outputs are latched at the logic

2Q

5

17

7D

3Q

6

16

7Q

levels set up at the D inputs.

A buffered output-enable (OE) input can be used

3D

7

15

6Q

4D

8

14

6D

to place the eight outputs in either a normal logic

9

10 11 12 13

state

(high

or

low

logic

levels)

or

the

4Q

GND

LE 5Q

5D

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines in bus-organized systems without need for

interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54ACT373 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ACT373 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (each latch)

		INPUTS		OUTPUT
				Q
	OE	LE	D
	L	H	H	H
	L	H	L	L
	L	L	X	Q0
	H	X	X	Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2000, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN54ACT373, SN74ACT373

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS544D ± OCTOBER 1995 ± REVISED JANUARY 2000

logic symbol²

logic diagram (positive logic)

		1		EN
OE
11
	LE			C1
3							2
	1D			1D			5	1Q
4								2Q
	2D
7							6
	3D							3Q
8							9
	4D							4Q
13							12
	5D							5Q
14							15
	6D							6Q
17							16
	7D							7Q
18							19
	8D							8Q

OE	1
LE	11
	C1	2
1D	3	1Q
	1D
	To Seven Other Channels

²This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 69°C/W
PW package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . ±65°C to 150°C

³ Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265