Texas Instruments SN74ABT273DBLE, SN74ABT273DBR, SN74ABT273DW, SN74ABT273DWR, SN74ABT273N Datasheet

	SN54ABT273, SN74ABT273
	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
	WITH CLEAR
	SCBS185B ± FEBRUARY 1991 ± REVISED JANUARY 1997
D State-of-the-Art EPIC-ΙΙB BiCMOS Design	SN54ABT273 . . . J OR W PACKAGE
Significantly Reduces Power Dissipation	SN74ABT273 . . . DB, DW, N, OR PW PACKAGE
	(TOP VIEW)

DLatch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17		CLR			1	20		VCC
D Typical VOLP (Output Ground Bounce) < 1 V		1Q			2	19		8Q
at VCC = 5 V, TA = 25°C		1D			3	18		8D
D High-Drive Outputs (±32-mA IOH, 64-mA IOL)		2D			4	17		7D
		2Q		5		16		7Q
D Package Options Include Plastic
		3Q				15		6Q
Small-Outline (DW), Shrink Small-Outline				6
		3D				14		6D
(DB), and Thin Shrink Small-Outline (PW)				7
		4D				13		5D
Packages, Ceramic Chip Carriers (FK),				8
		4Q				12		5Q
Plastic (N) and Ceramic (J) DIPs, and			9
Ceramic Flat (W) Package	GND		10			11		CLK

description

SN54ABT273 . . . FK PACKAGE

The 'ABT273 are 8-bit positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. They are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D input signal has no effect at the output.

(TOP VIEW)

	1D	1Q	CLR	CC	8Q
				V
2D	3	2	1	20 19		8D
	4				18
2Q	5				17	7D
3Q	6				16	7Q
3D	7				15	6Q
4D	8				14	6D
	9	10 11 12 13
	4Q	GND	CLK	5Q	5D

The SN54ABT273 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ABT273 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (each flip-flop)

		INPUTS		OUTPUT
		CLK	D	Q
	CLR
	L	X	X	L
	H	↑	H	H
	H	↑	L	L
	H	H or L	X	Q0

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN54ABT273, SN74ABT273

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR

SCBS185B ± FEBRUARY 1991 ± REVISED JANUARY 1997

logic symbol²

	1		R
CLR
11
CLK				C1
3						2
1D			1D				1Q
4						5
2D							2Q
7						6
3D							3Q
8						9
4D							4Q
						12
13							5Q
5D
						15
14							6Q
6D
17						16
7D							7Q
18						19
8D							8Q

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)
	1D	2D	3D	4D	5D	6D	7D	8D
11	3	4	7	8	13	14	17	18
CLK	CLK(I)
	1D	1D	1D	1D	1D	1D	1D	1D
	C1	C1	C1	C1	C1	C1	C1	C1
	R	R	R	R	R	R	R	R
1	R
CLR
		2	5	6	9	12	15	16	19
		1Q	2Q	3Q	4Q	5Q	6Q	7Q	8Q

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7	V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . .	±0.5 V to 5.5	V
Current into any output in the low state, IO: SN54ABT273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 96 mA
SN74ABT273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 115°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 128°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±65°C to 150°C

³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2.The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265