Texas Instruments SN74ACT7807-15PAG, SN74ACT7807-15PM, SN74ACT7807-20FN, SN74ACT7807-20PAG, SN74ACT7807-25FN Datasheet

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	SN74ACT7807
	2048	×9
	CLOCKED FIRST-IN, FIRST-OUT MEMORY
	SCAS200D ± JANUARY 1991 ± REVISED APRIL 1998

D Free-Running Read and Write Clocks Can	D Input-Ready, Output-Ready, and Half-Full
Be Asynchronous or Coincident	Flags
D Read and Write Operations Synchronized	D Cascadable in Word Width and/or Word
to Independent System Clocks	Depth
D Input-Ready Flag Synchronized to Write	D Fast Access Times of 12 ns With a 50-pF
Clock	Load
D Output-Ready Flag Synchronized to Read	D Data Rates up to 67 MHz
Clock	D 3-State Outputs
D 2048 Words by 9 Bits	D Package Options Include 44-Pin Plastic
D Low-Power Advanced CMOS Technology	Leaded Chip Carrier (FN) and 64-Pin Thin
D Programmable Almost-Full/Almost-Empty	Quad Flat (PAG, PM) Packages
D Programmable Almost-Full/Almost-Empty

Flag

description

The SN74ACT7807 is a 2048-word by 9-bit FIFO with high speed and fast access times. It processes data at rates up to 67 MHz and access times of 12 ns in a bit-parallel format. Data outputs are noninverting with respect to the data inputs. Expansion is easily accomplished in both word width and word depth.

The write-clock (WRTCLK) and read-clock (RDCLK) inputs should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when the write-enable (WRTEN1/DP9, WRTEN2) inputs are high and the input-ready (IR) flag output is high. Data is read from memory on the rising edge of RDCLK when the read-enable (RDEN1, RDEN2) and output-enable (OE) inputs are high and the output-ready (OR) flag output is high. The first word written to memory is clocked through to the output buffer regardless of the levels on RDEN1, RDEN2, and OE. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronous to WRTCLK and RDCLK. RESET must be asserted while at least four WRTCLK and four RDCLK cycles occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.

The SN74ACT7807 is characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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SN74ACT7807 2048 ×9

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS200D ± JANUARY 1991 ± REVISED APRIL 1998

FN PACKAGE (TOP VIEW)

AF/AE

GND

PEN

RESET

GND

VCC

GND

VCC

GND

18 19 20 21 22 23 24 25 26 27 28

GND

WRTCLK

WRTEN1/DP9

WRTEN2

RDEN2

RDEN1

RDCLK

PAG OR PM PACKAGE

(TOP VIEW)

GND

Q7 NC

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

GND

VCC

GND

VCC

RDCLK

RDEN1

VCC

RDEN2

RESET

PEN

GND

WRTEN2

GND

WRTEN1/DP9

AF/AE

WRTCLK

GND

VCC

GND

VCC

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

GND

D8 NC

NC ± No internal connection

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN74ACT7807 2048 ×9

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS200D ± JANUARY 1991 ± REVISED APRIL 1998

logic symbol²

FIFO 2048 × 9

SN74ACT7807

RESET

WRTCLK

WRTEN1/DP9

IN RDY

WRTEN

WRTEN2

HALF FULL

ALMOST FULL/EMPTY

AF/AE

RDCLK

OUT RDY

EN1

RDEN1

RDEN

RDEN2

PEN

PROGRAM ENABLE

Data

Data 1

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the FN package.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Texas Instruments SN74ACT7807-15PAG, SN74ACT7807-15PM, SN74ACT7807-20FN, SN74ACT7807-20PAG, SN74ACT7807-25FN Datasheet

SN74ACT7807 2048 ×9

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS200D ± JANUARY 1991 ± REVISED APRIL 1998

functional block diagram

OE
D0±D8
RDCLK			Location 1
RDCLK	Synchronous	Read	Location 2
RDEN1	Read	Read	Location 2
RDEN1	Read	Pointer
RDEN2	Control	Pointer
RDEN2	Control
			2048 × 9 RAM
WRTCLK	Synchronous	Write
WRTEN1/DP9	Write	Write
WRTEN1/DP9	Write	Pointer	Location 2047
WRTEN2	Control	Pointer	Location 2047
WRTEN2	Control		Location 2048
			Location 2048
			Register	Q0 ± Q8
	Reset	Status-		OR
	Reset	Flag
	Logic	Flag
RESET	Logic	Logic		IR
RESET		Logic		IR
PEN				HF
PEN				AF/AE
				AF/AE

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

		SN74ACT7807
		2048 ×9
		CLOCKED FIRST-IN, FIRST-OUT MEMORY
		SCAS200D ± JANUARY 1991 ± REVISED APRIL 1998

		Terminal Functions

TERMINAL	I/O	DESCRIPTION
NAME	I/O	DESCRIPTION
NAME

		Almost-full/almost-empty flag. Depth offset values can be programmed for AF/AE or the default value of 256 can
AF/AE	O	be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contains
		X or fewer words or (2048 ± Y) or more words. AF/AE is high after reset.

D0±D8	I	Nine-bit data input port

HF	O	Half-full flag. HF is high when the FIFO memory contains 1024 or more words. HF is low after reset.

		Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the FIFO is full and
IR	O	writes are disabled. IR is low during reset and goes high on the second low-to-high transition of WRTCLK after
		reset.

OE	I	Output enable. When OE, RDEN1, RDEN2 and OR are high, data is read from the FIFO on a low-to-high transition
OE	I	of RDCLK. When OE is low, reads are disabled and the data outputs are in the high-impedance state.


		Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FIFO is empty
OR	O	and reads are disabled. Ready data is present on Q0±Q17 when OR is high. OR is low during reset and goes high
		on the third low-to-high transition of RDCLK after the first word is loaded to empty memory.

	I	Program enable. After reset and before the first word is written to the FIFO, the binary value on D0±D8 and DP9
PEN
PEN		is latched as an AF/AE offset value when PEN is low and WRTCLK is high.


		Nine-bit data output port. After the first valid write to empty memory, the first word is output on Q0±Q8 on the third
Q0±Q8	O	rising edge of RDCLK. OR also is asserted high at this time to indicate ready data. When OR is low, the last word
		read from the FIFO is present on Q0±Q8.

		Read clock. RDCLK is a continuous clock and can be asynchronous or coincident to WRTCLK. A low-to-high
RDCLK	I	transition of RDCLK reads data from memory when RDEN1, RDEN2, OE, and OR are high. OR is synchronous
		to the low-to-high transition of RDCLK.

RDEN1	I	Read enables. When RDEN1, RDEN2, OE, and OR are high, data is read from the FIFO on the low-to-high
RDEN2	I	transition of RDCLK.
RDEN2		transition of RDCLK.

	I	Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of WRTCLK must
RESET
RESET		occur while RESET is low. This sets HF, IR, and OR low and AF/AE high.


		Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A low-to-high
WRTCLK	I	transition of WRTCLK writes data to memory when WRTEN1/DP9, WRTEN2, and IR are high. IR is synchronous
		to the low-to-high transition of WRTCLK.

		Write enable/data pin 9. When WRTEN1/DP9, WRTEN2, and IR are high, data is written to the FIFO on a
WRTEN1/DP9	I	low-to-high transition of WRTCLK. When programming an AF/AE offset value, WRTEN1/DP9 is used as the
		most-significant data bit.

WRTEN2	I	Write enable. When WRTEN1/DP9, WRTEN2, and IR are high, data is written to the FIFO on a low-to-high
WRTEN2	I	transition of WRTCLK.
		transition of WRTCLK.

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