Texas Instruments SN74AHC374DBR, SN74AHC374DGVR, SN74AHC374DW, SN74AHC374DWR, SN74AHC374N Datasheet

		SN54AHC374, SN74AHC374
	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
					WITH 3-STATE OUTPUTS
	SCLS240G ± OCTOBER 1995 ± REVISED JANUARY 2000
D EPIC (Enhanced-Performance Implanted	SN54AHC374 . . . J OR W PACKAGE
CMOS) Process	SN74AHC374 . . . DB, DGV, DW, N, OR PW PACKAGE
D Operating Range 2-V to 5.5-V VCC				(TOP VIEW)
D 3-State Outputs Drive Bus Lines Directly		OE			1	20		VCC
D Latch-Up Performance Exceeds 250 mA Per		1Q			2	19		8Q
JESD 17		1D			3	18		8D
D ESD Protection Exceeds 2000 V Per		2D			4	17		7D
		2Q			5	16		7Q
MIL-STD-883, Method 3015; Exceeds 200 V
		3Q			6	15		6Q
Using Machine Model (C = 200 pF, R = 0)
		3D			7	14		6D
D Package Options Include Plastic
		4D			8	13		5D
Small-Outline (DW), Shrink Small-Outline
		4Q			9	12		5Q
(DB), Thin Very Small-Outline (DGV), Thin
	GND				10	11		CLK
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic	SN54AHC374 . . . FK PACKAGE
(J) DIPs				(TOP VIEW)

description

The 'AHC374 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels of the data

(D) inputs.

	1D	1Q	OE	CC	8Q
				V
2D	3	2	1	20 19		8D
	4				18
2Q	5				17	7D
3Q	6				16	7Q
3D	7				15	6Q
4D	8				14	6D
	9	10 11 12 13
	4Q	GND	CLK	5Q	5D

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54AHC374 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74AHC374 is characterized for operation from ±40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2000, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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SN54AHC374, SN74AHC374

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCLS240G ± OCTOBER 1995 ± REVISED JANUARY 2000

FUNCTION TABLE (each flip-flop)

		INPUTS		OUTPUT
		CLK	D	Q
	OE
	L	↑	H	H
	L	↑	L	L
	L	H or L	X	Q0
	H	X	X	Z

logic symbol²

			1		EN
		OE
	11					C1
	CLK
	3							2
					1D				1Q
		1D
	4							5
		2D							2Q
	7							6
		3D							3Q
	8							9
		4D							4Q
	13							12
		5D							5Q
	14							15
		6D							6Q
	17							16
		7D							7Q
	18							19
		8D							8Q

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

OE	1
CLK	11
		C1	2
1D	3	1D	1Q
		To Seven Other Channels

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54AHC374, SN74AHC374

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCLS240G ± OCTOBER 1995 ± REVISED JANUARY 2000

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±0.5 V to 7	V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±0.5 V to 7	V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.5 V to VCC + 0.5	V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ±75 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 92°C/W
DW package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 69°C/W
PW package . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . ±65°C to 150°C

² Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 3)

			SN54AHC374		SN74AHC374		UNIT
			MIN	MAX	MIN	MAX
VCC	Supply voltage		2	5.5	2	5.5	V
		VCC = 2 V	1.5		1.5
VIH	High-level input voltage	VCC = 3 V	2.1		2.1		V
		VCC = 5.5 V	3.85		3.85
		VCC = 2 V		0.5		0.5
VIL	Low-level input voltage	VCC = 3 V		0.9		0.9	V
		VCC = 5.5 V		1.65		1.65
VI	Input voltage		0	5.5	0	5.5	V
VO	Output voltage		0	VCC	0	VCC	V
		VCC = 2 V		±50		±50	mA
IOH	High-level output current	VCC = 3.3 V ± 0.3 V		±4		±4	mA
		VCC = 5 V ± 0.5 V		±8		±8
		VCC = 2 V		50		50	mA
IOL	Low-level output current	VCC = 3.3 V ± 0.3 V		4		4	mA
		VCC = 5 V ± 0.5 V		8		8
t/Δv Input transition rise or fall rate		VCC = 3.3 V ± 0.3 V		100		100	ns/V
		VCC = 5 V ± 0.5 V		20		20
TA	Operating free-air temperature		±55	125	±40	85	°C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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