Analog Devices AD7863BR-3, AD7863BR-10, AD7863ARS-3, AD7863ARS-2, AD7863ARS-10 Datasheet

a		Simultaneous Sampling
		Dual 175 kSPS 14-Bit ADC
		AD7863

FEATURES

Two Fast 14-Bit ADCs

Four Input Channels

Simultaneous Sampling and Conversion 5.2 s Conversion Time

Single Supply Operation

Selection of Input Ranges10 V for AD7863-102.5 V for AD7863-3

0 V to 2.5 V for AD7863-2 High Speed Parallel Interface Low Power, 70 mW Typ

Power Saving Mode, 105 W Max

Overvoltage Protection on Analog Inputs 14-Bit Lead Compatible Upgrade to AD7862

APPLICATIONS

AC Motor Control

Uninterrupted Power Supplies

Data Acquisition Systems

Communications

GENERAL DESCRIPTION

The AD7863 is a high speed, low power, dual 14-bit A/D converter that operates from a single +5 V supply. The part contains two 5.2 s successive approximation ADCs, two track/hold amplifiers, an internal +2.5 V reference and a high speed parallel interface. Four analog inputs are grouped into two channels (A and B) selected by the A0 input. Each channel has two inputs (VA1 and VA2 or VB1 and VB2), which can be sampled and converted simultaneously thus preserving the relative phase information of the signals on both analog inputs. The part accepts an analog input range of ±10 V (AD7863-10), ±2.5 V (AD7863-3) and

0 V–2.5 V (AD7863-2). Overvoltage protection on the analog inputs for the part allows the input voltage to go to ±17 V, ±7 V or +7 V respectively, without causing damage.

A single conversion start signal (CONVST) simultaneously places both track/holds into hold and initiates conversion on both channels. The BUSY signal indicates the end of conversion and at this time the conversion results for both channels are available to be read. The first read after a conversion accesses the result from VA1 or VB1, while the second read accesses the result from VA2 or VB2, depending on whether the multiplexer select A0 is low or high respectively. Data is read from the part via a 14-bit parallel data bus with standard CS and RD signals.

In addition to the traditional dc accuracy specifications such as linearity, gain and offset errors, the part is also specified for dynamic performance parameters including harmonic distortion and signal-to-noise ratio.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

VREF

VDD

2k	+2.5V
	REFERENCE

AD7863

VA1	SIGNAL	TRACK/
	SCALING	HOLD	14-BIT
	MUX
			ADC
VB1	SIGNAL
	SCALING		DB0
			OUTPUT
	SIGNAL	TRACK/	LATCH
VA2			DB13
	SCALING	HOLD	14-BIT
	MUX		ADC
VB2	SIGNAL		CS
	SCALING
			RD
	CONVERSION		CLOCK
	CONTROL LOGIC
	A0 BUSY CONVST		AGND AGND DGND

The AD7863 is fabricated in Analog Devices’ Linear Compatible CMOS (LC2MOS) process, a mixed technology process that combines precision bipolar circuits with low power CMOS logic. It is available in 28-lead SOIC and SSOP.

PRODUCT HIGHLIGHTS

1.The AD7863 features two complete ADC functions allowing simultaneous sampling and conversion of two channels.

Each ADC has a two-channel input mux. The conversion result for both channels is available 5.2 s after initiating conversion.

2.The AD7863 operates from a single +5 V supply and consumes 70 mW typ. The automatic power-down mode, where the part goes into power down once conversion is complete and “wakes up” before the next conversion cycle, makes the AD7863 ideal for battery-powered or portable applications.

3.The part offers a high speed parallel interface for easy connection to microprocessors, microcontrollers and digital signal processors.

4.The part is offered in three versions with different analog

input ranges. The AD7863-10 offers the standard industrial input range of ±10 V; the AD7863-3 offers the common signal processing input range of ±2.5 V, while the AD7863-2 can be used in unipolar 0 V–2.5 V applications.

5.The part features very tight aperture delay matching between the two input sample and hold amplifiers.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	World Wide Web Site: http://www.analog.com
Fax: [phone]	© Analog Devices, Inc., 1999

		(VDD = +5 V 5%, AGND = DGND = 0 V, REF = Internal. All specifications TMIN to TMAX
AD7863–SPECIFICATIONS unless otherwise noted.)
		A	B
	Parameter	Version1	Version1	Units	Test Conditions/Comments
	SAMPLE AND HOLD
	–3 dB Small Signal Bandwidth	7	7	MHz typ
	Aperture Delay2	35	35	ns max
	Aperture Jitter2	50	50	ps typ
	Aperture Delay Matching2	350	350	ps max
	DYNAMIC PERFORMANCE3				f	IN	= 80.0 kHz, f = 175 kSPS
	Signal to (Noise + Distortion) Ratio4						S
	@ +25°C	78	78	dB min
	TMIN to TMAX	77	77	dB min
	Total Harmonic Distortion4	–82	–82	dB max	Typically –87 dB
	Peak Harmonic or Spurious Noise4	–82	–82	dB max	Typically –90 dB
	Intermodulation Distortion4				fa = 49 kHz, fb = 50 kHz
	2nd Order Terms	–93	–93	dB typ
	3rd Order Terms	–89	–89	dB typ
	Channel-to-Channel Isolation4	–86	–86	dB typ	fIN = 50 kHz Sine Wave
	DC ACCURACY				Any Channel
	Resolution	14	14	Bits
	Minimum Resolution for Which No
	Missing Codes are Guaranteed	14	14	Bits
	Relative Accuracy4	±2.5	±2	LSB max
	Differential Nonlinearity4	+2 to –1	+2 to –1	LSB max
	AD7863-10, AD7863-3	±10	±8
	Positive Gain Error4			LSB max
	Positive Gain Error Match4	10	10	LSB max
	Negative Gain Error4	±10	±8	LSB max
	Negative Gain Error Match4	10	10	LSB max
	Bipolar Zero Error	±10	±8	LSB max
	Bipolar Zero Error Match	8	6	LSB max
	AD7863-2	±14
	Positive Gain Error4			LSB max
	Positive Gain Error Match4	16		LSB max
	Unipolar Offset Error	±14		LSB max
	Unipolar Offset Error Match	10		LSB max
	ANALOG INPUTS
	AD7863-10	±10	±10
	Input Voltage Range			Volts
	Input Resistance	9	9	kΩ typ
	AD7863-3	±2.5	±2.5
	Input Voltage Range			Volts
	Input Resistance	3	3	kΩ typ
	AD7863-2
	Input Voltage Range	+2.5	+2.5	Volts
	Input Current	100	100	nA max
	REFERENCE INPUT/OUTPUT				2.5 V ± 5%
	REF IN Input Voltage Range	2.375/2.625	2.375/2.625
	REF IN Input Current	±100	±100	µA max
	REF OUT Output Voltage	2.5	2.5	V nom
	REF OUT Error @ +25°C	±10	±10	mV max
	REF OUT Error TMIN to TMAX	±20	±20	mV max
	REF OUT Temperature Coefficient	25	25	ppm/°C typ
	LOGIC INPUTS				VDD = 5 V ± 5%
	Input High Voltage, VINH	2.4	2.4	V min
	Input Low Voltage, VINL	0.8	0.8	V max	VDD = 5 V ± 5%
	Input Current, IIN	±10	±10	µA max
	Input Capacitance, C 5	10	10	pF max
	IN

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				AD7863
	A	B
Parameter	Version1	Version1	Units	Test Conditions/Comments
LOGIC OUTPUTS				ISOURCE = 200 A
Output High Voltage, VOH	4.0	4.0	V min
Output Low Voltage, VOL	0.4	0.4	V max	ISINK = 1.6 mA
DB11–DB0	±10	±10	A max
Floating-State Leakage Current
Floating-State Capacitance5	10	10	pF max
Output Coding
AD7863-10, AD7863-3				Twos Complement
AD7863-2				Straight (Natural) Binary
CONVERSION RATE
Conversion Time			s max
Mode 1 Operation	5.2	5.2		For Both Channels
Mode 2 Operation6	10.0	10.0	s max	For Both Channels
Track/Hold Acquisition Time4, 7	0.5	0.5	s max
POWER REQUIREMENTS				±5% for Specified Performance
VDD	+5	+5	V nom
IDD
Normal Mode (Mode 1)
AD7863-10	17	17	mA max
AD7863-3	15	15	mA max
AD7863-2	10	10	mA max
Power-Down Mode (Mode 2)
IDD @ +25°C8	20	20	A max	40 nA typ. Logic Inputs = 0 V or VDD
Power Dissipation
Normal Mode (Mode 1)
AD7863-10	89.25	89.25	mW max	VDD = 5.25 V, Typically 70 mW
AD7863-3	78.75	78.75	mW max	VDD = 5.25 V, Typically 70 mW
AD7863-2	52.5	52.5	mW max	VDD = 5.25 V, Typically 45 mW
Power-Down Mode @ +25°C	105	105	W max	Typically 210 nW, VDD = 5.25 V

NOTES

1Temperature ranges are as follows: A, B Versions: –40°C to +85°C. 2Sample tested during initial release.

3Applies to Mode 1 operation. See section on operating modes. 4See Terminology.

5Sample tested @ +25°C to ensure compliance.

6This 10 µs includes the “wake-up” time from standby. This “wake-up” time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of CONVST, for a narrow CONVST pulsewidth the conversion time is effectively the “wake-up” time plus conversion time, hence 10 µs. This can be seen from Figure 6. Note that if the CONVST pulsewidth is greater than 5.2 µs, the effective conversion time will increase beyond 10 µs.

7Performance measured through full channel (multiplexer, SHA and ADC).

8For best dynamic performance of the AD7863, ATE device testing has to be performed with power supply decoupling in place. In the AD7863 power-down mode of operation, the leakage current associated with these decoupling capacitors is greater than that of the AD7863 supply current. Therefore the 40 nA typical figure shown is a characterized and guaranteed by design figure, which reflects the supply current of the AD7863 without decoupling in place. The max figure shown in the Conditions/ Comments column reflects the AD7863 with supply decoupling in place—0.1 µF in parallel with a 10 µF disc ceramic capacitors on the VDD pin and 2 × 0.1 µF disc ceramic capacitors on the VREF pin, in both cases to the AGND plane.

Specifications subject to change without notice.

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AD7863

TIMING CHARACTERISTICS1, 2

(VDD = +5 V 5%, AGND = DGND = 0 V, REF = Internal. All specifications TMIN to TMAX unless otherwise noted.)

	A, B
Parameter	Versions	Units	Test Conditions/Comments
tCONV	5.2	s max	Conversion Time
tACQ	0.5	s max	Acquisition Time
Parallel Interface
t1	0	ns min	CS to RD Setup Time
t2	0	ns min	CS to RD Hold Time
t3	35	ns min	CONVST Pulsewidth
t4	45	ns min	Read Pulsewidth
t53	30	ns min	Data Access Time after Falling Edge of RD
t64	5	ns min	Bus Relinquish Time after Rising Edge of RD
	30	ns max
t7	10	ns min	Time Between Consecutive Reads
t8	400	ns min	Quiet Time

NOTES

1Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V. 2See Figure 1.

3Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.0 V.

4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.

Specifications subject to change without notice.

		tACQ
		t8
CONVST
	t3
BUSY
A0	tCONV = 5.2 s
CS
	t1	t2		t7
	t4
RD
	t5	t6
DATA	VA1	VA2	VB1	VB2

Figure 1. Timing Diagram

1.6mA

TO OUTPUT PIN

50pF

200 A

Figure 2. Load Circuit for Access Time and Bus Relinquish Time

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AD7863

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Analog Input Voltage to AGND

AD7863-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±17 V AD7863-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V AD7863-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V Reference Input Voltage to AGND . . . .–0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V Digital Output Voltage to DGND . . . . –0.3 V to VDD + 0.3 V

Operating Temperature Range

Commercial (A, B Version) . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model	Input Ranges	Relative Accuracy	Temperature Range	Package Options*
AD7863AR-10	±10 V	±2.5 LSB	–40°C to +85°C	R-28
AD7863BR-10	±10 V	±2.0 LSB	–40°C to +85°C	R-28
AD7863ARS-10	±10 V	±2.5 LSB	–40°C to +85°C	RS-28
AD7863AR-3	±2.5 V	±2.5 LSB	–40°C to +85°C	R-28
AD7863ARS-3	±2.5 V	±2.5 LSB	–40°C to +85°C	RS-28
AD7863BR-3	±2.5 V	±2.0 LSB	–40°C to +85°C	R-28
AD7863AR-2	0 V to 2.5 V	±2.5 LSB	–40°C to +85°C	R-28
AD7863ARS-2	0 V to 2.5 V	±2.5 LSB	–40°C to +85°C	RS-28

*R = Small Outline (SOIC), RS = Shrink Small Outline (SSOP).

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7863 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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AD7863

		PIN FUNCTION DESCRIPTIONS
Pin	Mnemonic	Description
1–6	DB12–DB7	Data Bit 12 to Data Bit 7. Three-state TTL outputs.
7	DGND	Digital Ground. Ground reference for digital circuitry.
8	CONVST	Convert Start Input. Logic Input. A high to low transition on this input puts both track/holds into their hold
		mode and starts conversion on both channels.
9–15	DB6–DB0	Data Bit 6 to Data Bit 0. Three-state TTL outputs.
16	AGND	Analog Ground. Ground reference for Mux, track/hold, reference and DAC circuitry.
17	VB2	Input Number 2 of Channel B. Analog Input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3)
		and 0 V–2.5 V (AD7863-2).
18	VA2	Input Number 2 of Channel A. Analog Input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3)
		and 0 V–2.5 V (AD7863-2).
19	VREF	Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
		output reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this
		appears at the pin.
20	A0	Multiplexer Select. This input is used in conjunction with CONVST to determine on which pair of channels
		the conversion is to be performed. If A0 is low when the conversion is initiated then channels VA1, VA2 will
		be selected. If A0 is high when the conversion is initiated, channels VB1, VB2 will be selected.
21	CS	Chip Select Input. Active low logic input. The device is selected when this input is active.
22	RD	Read Input. Active low logic input. This input is used in conjunction with CS low to enable the data out-
		puts and read a conversion result from the AD7863.
23	BUSY	Busy Output. The busy output is triggered high by the falling edge of CONVST and remains high until
		conversion is completed.
24	VDD	Analog and Digital Positive Supply Voltage, +5.0 V ± 5%.
25	VA1	Input Number 1 of Channel A. Analog Input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3)
		and 0 V–2.5 V (AD7863-2).
26	VB1	Input Number 1 of Channel B. Analog Input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3)
		and 0 V–2.5 V (AD7863-2).
27	AGND	Analog Ground. Ground reference for Mux, track/hold, reference and DAC circuitry.
28	DB13	Data Bit 13 (MSB). Three-state TTL output. Output coding is twos complement for the AD7863-10 and
		AD7863-3. Output coding is straight (natural) binary for the AD7863-2.
		PIN CONFIGURATION
		DB12						DB13
			1				28
		DB11						AGND
			2				27
		DB10						VB1
			3				26
		DB9						VA1
			4				25
		DB8						VDD
			5				24
		DB7						BUSY
			6	AD7863			23
		DGND
			7	TOP VIEW			22	RD
				(Not to Scale)
		CONVST	8				21	CS
		DB6						A0
			9				20
								VREF
		DB5	10				19
		DB4	11				18	VA2
		DB3	12				17	VB2
		DB2	13				16	AGND
		DB1	14				15	DB0

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