Analog Devices AD779TD, AD779SD, AD779KN, AD779KD, AD779JN Datasheet

a		14-Bit 128 kSPS
		Complete Sampling ADC
		AD779*
	FEATURES	FUNCTIONAL BLOCK DIAGRAM
	AC and DC Characterized and Specified (K, B, T
	Grades)
	128k Conversions per Second
	1 MHz Full Power Bandwidth
	500 kHz Full Linear Bandwidth
	80 dB S/N+D (K, B, T Grades)
	Twos Complement Data Format (Bipolar Mode)
	Straight Binary Data Format (Unipolar Mode)
	10 MV Input Impedance
	16-Bit Bus Interface (See AD679 for 8-Bit Interface)
	Onboard Reference and Clock
	10 V Unipolar or Bipolar Input Range
	MIL-STD-883 Compliant Versions Available

PRODUCT DESCRIPTION

The AD779 is a complete, multipurpose 14-bit monolithic analog-to-digital converter, consisting of a sample-hold amplifier (SHA), a microprocessor compatible bus interface, a voltage reference and clock generation circuitry.

The AD779 is specified for ac (or “dynamic”) parameters such as S/N+D ratio, THD and IMD which are important in signal processing applications. In addition, the AD779K, B and T grades are fully specified for dc parameters which are important in measurement applications.

The 14 data bits are accessed by a 16-bit bus in a single read operation. Data format is straight binary for unipolar mode and twos complement binary for bipolar mode. The input has a fullscale range of 10 V with a full power bandwidth of 1 MHz and a full linear bandwidth of 500 kHz. High input impedance (10 MΩ) allows direct connection to unbuffered sources without signal degradation.

This product is fabricated on Analog Devices’ BiMOS process, combining low power CMOS logic with high precision, low noise bipolar circuits; laser-trimmed thin-film resistors provide high accuracy. The converter utilizes a recursive subranging algorithm which includes error correction and flash converter circuitry to achieve high speed and resolution.

The AD779 operates from +5 V and ±12 V supplies and dissipates 560 mW (typ). Twenty-eight-pin plastic DIP and ceramic DIP packages are available.

*Protected by U.S. Patent Numbers 4,804,960; 4,814,767; 4,833,345;

4,250,445; 4,808,908; RE30,586.

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

PRODUCT HIGHLIGHTS

l.COMPLETE INTEGRATION: The AD779 minimizes external component requirements by combining a high speed sample-hold amplifier (SHA), ADC, 5 V reference, clock and digital interface on a single chip. This provides a fully specified sampling A/D function unattainable with discrete designs.

2.SPECIFICATIONS: The AD779K, B and T grades provide fully specified and tested ac and dc parameters. The AD779J, A and S grades are specified and tested for ac parameters; dc accuracy specifications are shown as typicals. DC specifications (such as INL, gain and offset) are important in control and measurement applications. AC specifications (such as S/N+D ratio, THD and IMD) are of value in signal processing applications.

3.EASE OF USE: The pinout is designed for easy board layout, and the single cycle read output provides compatibility with 16-bit buses. Factory trimming eliminates the need for calibration modes or external trimming to achieve rated performance.

4.RELIABILITY: The AD779 utilizes Analog Devices’ monolithic BiMOS technology. This ensures long term reliability compared to multichip and hybrid designs.

5.The AD779 is available in versions compliant with MIL- STD-883. Refer to the Analog Devices Military Products Databook or current AD779/883B data sheet for detailed specifications.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: [phone] Fax: [phone]

AD779–SPECIFICATIONS

(TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%, fSAMPLE = 128 kSPS,

AC SPECIFICATIONS flN = 10.009 kHz unless otherwise noted)1

AD779J/A/S

AD779K/B/T

Parameter

Min

Typ

Max

Min

Typ

Max

Units

SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO

–0.5 dB Input (Referred to 0 dB Input)

78

79

80

81

dB

–20 dB Input (Referred to –20 dB Input)

58

59

60

61

dB

–60 dB Input (Referred to –60 dB Input)

18

19

20

21

dB

TOTAL HARMONIC DISTORTION (THD)

@ +25°C

–90

–84

–90

–84

dB

0.003

0.006

0.003

0.006

%

TMIN to TMAX

–88

–82

–88

–82

dB

0.004

0.008

0.004

0.008

%

PEAK SPURIOUS OR PEAK HARMONIC COMPONENT

–90

–84

–90

–84

dB

FULL POWER BANDWIDTH

1

1

MHz

FULL LINEAR BANDWIDTH

500

500

kHz

INTERMODULATION DISTORTION (IMD)2

2nd Order Products

–90

–84

–90

–84

dB

3rd Order Products

–90

–84

–90

–84

dB

DIGITAL SPECIFICATIONS (All device types TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)

Parameter

Test Conditions

Min

Max

Units

LOGIC INPUTS

VIH

High Level Input Voltage

2.0

VDD

V

VIL

Low Level Input Voltage

0

0.8

V

IIH

High Level Input Current

VIN = VDD

–10

+10

μA

IIL

Low Level Input Current

VIN = 0 V

–10

+10

μA

CIN

Input Capacitance

10

pF

LOGIC OUTPUTS

VOH

High Level Output Voltage

IOH = 0.1 mA

4.0

V

VOL

IOH = 0.5 mA

2.4

V

Low Level Output Voltage

IOL = 1.6 mA

0.4

V

IOZ

High Z Leakage Current

VIN = VDD

–10

+10

μA

COZ

High Z Output Capacitance

10

pF

NOTES

1fIN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a –0 dB (9.997 V p-p) input signal unless otherwise noted.

2fA = 9.08 kHz, fB = 9.58 kHz, with fSAMPLE = 128 kSPS. Specifications subject to change without notice.

–2–

REV. B

								AD779
DC SPECIFICATIONS (TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10% unless otherwise noted)
		AD779J/A/S			AD779K/B/T
Parameter	Min	Typ	Max	Min	Typ	Max		Units
TEMPERATURE RANGE								°C
J, K Grades	0		+70	0		+70
A, B Grades	–40		+85	–40		+85		°C
S, T Grades	–55		+125	–55		+125		°C
ACCURACY
Resolution	14	±2		14	±1	±2		Bits
Integral Nonlinearity (INL)								LSB
Differential Nonlinearity (DNL)	14			14				Bits
Unipolar Zero Error1 (@ +25°C)		0.08			0.05	0.07		% FSR*
Bipolar Zero Error1 (@ +25°C)		0.08			0.05	0.07		% FSR
Gain Error1, 2 (@ +25°C)		0.12			0.09	0.11		% FSR
Temperature Drift
Unipolar Zero3
J, K Grades		0.04			0.04	0.05		% FSR
A, B Grades		0.05			0.05	0.07		% FSR
S, T Grades		0.09			0.09	0.10		% FSR
Bipolar Zero3
J, K Grades		0.02			0.02	0 04		% FSR
A, B Grades		0.04			0.04	0.06		% FSR
S, T Grades		0.08			0.08	0.09		% FSR
Gain3
J, K Grades		0.09			0.09	0.11		% FSR
A, B Grades		0.10			0.10	0.16		% FSR
S, T Grades		0.20			0.20	0.25		% FSR
Gain4
J, K Grades		0.04			0.04	0.05		% FSR
A, B Grades		0.05			0.05	0.07		% FSR
S, T Grades		0.09			0.09	0.10		% FSR
ANALOG INPUT
Input Ranges
Unipolar Mode	0		+10	0		+10		V
Bipolar Mode	–5		+5	–5		+5		V
Input Resistance		10			10			MΩ
Input Capacitance		10			10			pF
Input Settling Time			1.5			1.5		μs
Aperture Delay		10			10			ns
Aperture Jitter		150			150			ps
INTERNAL VOLTAGE REFERENCE
Output Voltage5	4.98		5.02	4.98		5.02		V
External Load
Unipolar Mode			+1.5			+1.5		mA
Bipolar Mode			+0.5			+0.5		mA
POWER SUPPLIES
Power Supply Rejection
VCC = +12 V ± 5%		±6				±6		LSB
VEE = –12 V ± 5%		±6				±6		LSB
VDD = +5 V ± 10%		±6				±6		LSB
Operating Current		18	20		18	20		mA
ICC
IEE		25	34		25	34		mA
IDD		8	12		8	12		mA
Power Consumption		560	745		560	745		mW

NOTES

1Adjustable to zero. See Figures 5 and 6.

2Includes internal voltage reference error.

3Includes internal voltage reference drift.

4Excludes internal voltage reference drift.

5With maximum external load applied. *% FSR = percent of full-scale range.

Specifications subject to change without notice.

REV. B

–3–

AD779

TIMING SPECIFICATIONS

(All device types TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)

Parameter		Symbol	Min	Max	Units
Conversion Rate1		tCR		7.8	μs
Convert Pulse Width		tCP	0.097	3.0	μs
Aperture Delay		tAD	5	20	ns
Conversion Time		tC		6.3	μs
Status Delay		tSD	0	400	ns
Access Time2, 3		tBA	10	100	ns
Float Delay5			10	574	ns
		tFD	10	80	ns
Output Delay		tOD		0	ns
OE	Delay	tOE	20		ns
Read Pulse Width		tRP	100		ns
Conversion Delay		tCD	400		ns

NOTES

1Includes Acquisition Time.

2Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the data lines/EOC cross 2.0 V or 0.8 V. See Figure 4.

3COUT = 100 pF.

4COUT = 50 pF.

5Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the output voltage changes by 0.5 V. See Figure 4; COUT = 10 pF.

Specifications subject to change without notice.

Figure 3. EOC Timing

Figure 1. Conversion Timing

Figure 4. Load Circuit for Bus Timing Specifications

Figure 2. Output Timing

–4–

REV. B