Analog Devices AD8802ARU, AD8802AR, AD8802AN, AD8804ARU, AD8804AR Datasheet

a		12 Channel, 8-Bit TrimDACs
		with Power Shutdown
		AD8802/AD8804

FEATURES

Low Cost

Replaces 12 Potentiometers Individually Programmable Outputs 3-Wire SPI Compatible Serial Input

Power Shutdown <55 mWatts Including IDD & IREF

Midscale Preset, AD8802

Separate VREFL Range Setting, AD8804 +3 V to +5 V Single Supply Operation

APPLICATIONS

Automatic Adjustment

Trimmer Replacement

Video and Audio Equipment Gain and Offset Adjustment

Portable and Battery Operated Equipment

GENERAL DESCRIPTION

The 12-channel AD8802/AD8804 provides independent digitallycontrollable voltage outputs in a compact 20-lead package. This potentiometer divider TrimDAC® allows replacement of the mechanical trimmer function in new designs. The AD8802/ AD8804 is ideal for dc voltage adjustment applications.

Easily programmed by serial interfaced microcontroller ports, the AD8802 with its midscale preset is ideal for potentiometer replacement where adjustments start at a nominal value. Applications such as gain control of video amplifiers, voltage controlled frequencies and bandwidths in video equipment, geometric correction and automatic adjustment in CRT computer graphic displays are a few of the many applications ideally suited for these parts. The AD8804 provides independent control of both the top and bottom end of the potentiometer divider allowing a separate zero-scale voltage setting determined by the

VREFL pin. This is helpful for maximizing the resolution of devices with a limited allowable voltage control range.

Internally the AD8802/AD8804 contains 12 voltage-output digital-to-analog converters, sharing a common referencevoltage input.

TrimDAC is a registered trademark of Analog Devices, Inc.

FUNCTIONAL BLOCK DIAGRAM

CS				AD8802/AD8804		VDD
CLK						VREFH
					DAC
				D7		O1
					1
						O2
					DAC
			EN			O3
		D11			REG
						O4
		D10	ADDR	D0	#1
		D9	DEC		R	O5
		D8				O6
		D7				O7
	SER					O8
						O9
	REG
SDI						O10
	D	D0		D7	DAC	O11
						O12
					12
			8		DAC
					REG
				D0	#12
					R
SHDN
	GND			RS	VREFL
			(AD8802 ONLY)		(AD8804 ONLY)

Each DAC has its own DAC latch that holds its output state. These DAC latches are updated from an internal serial-to- parallel shift register that is loaded from a standard 3-wire serial input digital interface. The serial-data-input word is

decoded where the first 4 bits determine the address of the DAC latches to be loaded with the last 8 bits of data. The AD8802/ AD8804 consumes only 10 μA from 5 V power supplies. In addition, in shutdown mode reference input current consumption is also reduced to 10 μA while saving the DAC latch settings for use after return to normal operation.

The AD8802/AD8804 is available in the 20-pin plastic DIP, the SOIC-20 surface mount package, and the 1 mm thin TSSOP-20 package.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

© Analog Devices, Inc., 1995

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: [phone] Fax: [phone]

(VDD = +3 V 6 10% or +5 V 6 10%, VREFH = +VDD, VREFL = 0 V, –408C

AD8802/AD8804–SPECIFICATIONS ≤TA ≤ +858C unless otherwise noted)

Parameter

Symbol

Conditions

Min

Typ1

Max

Units

STATIC ACCURACY

Specifications apply to all DACs

Resolution

N

8

±1/4

Bits

Differential Nonlinearity Error

DNL

Guaranteed Monotonic

–1

+1

LSB

Integral Nonlinearity Error

INL

–1.5

±1/2

+1.5

LSB

Full-Scale Error

GFSE

–1

1/2

+1

LSB

Zero Code Error

VZSE

–1

1/4

+1

LSB

DAC Output Resistance

ROUT

3

5

8

kΩ

Output Resistance Match

R/RO

1.5

%

REFERENCE INPUT

Voltage Range2

VREFH

0

VDD

V

VREFL

Pin Available on AD8804 Only

0

VDD

V

REFH Input Resistance

RREFH

Digital Inputs = 55H, VREFH = VDD

1.2

kΩ

REFL Input Resistance3

RREFL

Digital Inputs = 55H, VREFL = VDD

1.2

kΩ

Reference Input Capacitance3

CREF0

Digital Inputs all Zeros

32

pF

CREF1

Digital Inputs all Ones

32

pF

DIGITAL INPUTS

Logic High

VIH

VDD = +5 V

2.4

V

Logic Low

VIL

VDD = +5 V

0.8

V

Logic High

VIH

VDD = +3 V

2.1

V

Logic Low

VIL

VDD = +3 V

0.6

V

Input Current

IIL

VIN = 0 V or + 5 V

±1

μA

Input Capacitance3

CIL

5

pF

POWER SUPPLIES4

Power Supply Range

VDD Range

2.7

5.5

V

Supply Current (CMOS)

IDD

VIH = VDD or VIL = 0 V

0.01

10

μA

Supply Current (TTL)

IDD

VIH = 2.4 V or VIL = 0.8 V, VDD = +5.5 V

1

4

mA

Shutdown Current

IREFH

= 0

0.2

10

μA

SHDN

Power Dissipation

PDISS

VIH = VDD or VIL = 0 V, VDD = +5.5 V

55

μW

Power Supply Sensitivity

PSRR

VDD = +5 V ± 10%

0.001

0.002

%/%

DYNAMIC PERFORMANCE3

±1/2 LSB Error Band

μs

VOUT Settling Time

tS

0.6

Crosstalk

CT

Between Adjacent Outputs5

50

dB

SWITCHING CHARACTERISTICS3, 6

Input Clock Pulse Width

tCH, tCL

Clock Level High or Low

15

ns

Data Setup Time

tDS

5

ns

Data Hold Time

tDH

5

ns

CS

Setup Time

tCSS

10

ns

CS

High Pulse Width

tCSW

10

ns

Reset Pulse Width

tRS

90

ns

CLK Rise to

CS

Rise Hold Time

tCSH

20

ns

CS

Rise to Clock Rise Setup

tCS1

10

ns

NOTES

1Typicals represent average readings at +25°C.

2VREFH can be any value between GND and VDD, for the AD8804 VREFL can be any value between GND and VDD.

3Guaranteed by design and not subject to production test.

4Digital Input voltages VIN = 0 V or VDD for CMOS condition. DAC outputs unloaded. PDISS is calculated from (IDD × VDD).

5Measured at a VOUT pin where an adjacent VOUT pin is making a full-scale voltage change (f = 100 kHz).

6See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

Specifications subject to change without notice.

–2–

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AD8802/AD8804

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C, unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, + 8 V VREFX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD Digital Input Voltage to GND . . . . . . . . . . . . . . . . . 0 V, +8 V

Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C Maximum Junction Temperature (TJ MAX) . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Package Power Dissipation . . . . . . . . . . . . (TJ MAX – TA)/θJA Thermal Resistance θJA,

SOIC (SOL-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W P-DIP (N-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W TSSOP-20 (RU-20) . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W

AD8802 PIN DESCRIPTIONS

Pin Name Description

1 VREF Common DAC Reference Input

2O1 DAC Output #1, addr = 00002

3O2 DAC Output #2, addr = 00012

4O3 DAC Output #3, addr = 00102

5O4 DAC Output #4, addr = 00112

6O5 DAC Output #5, addr = 01002

7O6 DAC Output #6, addr = 01012

8SHDN Reference input current goes to zero. DAC

latch settings maintained

9	CS	Chip Select Input, Active Low. When CS
		returns high, data in the serial input register is
		decoded based on the address bits and loaded
		into the target DAC register
10	GND	Ground
11	CLK	Serial Clock Input, Positive Edge Triggered
12	SDI	Serial Data Input

13O7 DAC Output #7, addr = 01102

14O8 DAC Output #8, addr = 01112

15O9 DAC Output #9, addr = 10002

16O10 DAC Output #10, addr = 10012

17O11 DAC Output #11, addr = 10102

18O12 DAC Output #12, addr = 10112

19RS Asynchronous Preset to Midscale Output

	Setting. Loads all DAC Registers with 80H
20 VDD	Positive Power Supply, Specified for Operation
	at Both +3 V and +5 V

PIN CONFIGURATIONS

	VREFH	1		20	VDD	VREFH	1		20	VDD
	O1	2		19	RS	O1	2		19	O12
	O2	3		18	O12	O2	3		18	O11
					O11
	O3	4		17		O3	4		17	O10
								AD8804
	O4	5	AD8802	16	O10	O4	5		16	O9
			TOP VIEW					TOP VIEW
	O5	6		15	O9	O5	6		15	O8
			(Not to Scale)					(Not to Scale)
					O8
	O6	7		14		O6	7		14	O7
	SHDN	8		13	O7	SHDN	8		13	SDI
	CS	9		12	SDI	CS	9		12	CLK
	GND	10		11	CLK	GND	10		11	VREFL

AD8804 PIN DESCRIPTIONS

Pin

Name

Description

1

VREFH

Common High-Side DAC Reference Input

2

O1

DAC Output #1, addr = 00002

3

O2

DAC Output #2, addr = 00012

4

O3

DAC Output #3, addr = 00102

5

O4

DAC Output #4, addr = 00112

6

O5

DAC Output #5, addr = 01002

7

O6

DAC Output #6, addr = 01012

8

SHDN

Reference input current goes to zero DAC latch

settings maintained

9

CS

Chip Select Input, Active Low. When

CS

returns

high, data in the serial input register is decoded

based on the address bits and loaded input the

target DAC register

10

GND

Ground

11

VREFL

Common Low-Side DAC Reference Input

12

CLK

Serial Clock Input, Positive Edge Triggered

13

SDI

Serial Data Input

14

O7

DAC Output #7, addr = 01102

15

O8

DAC Output #8, addr = 01112

16

O9

DAC Output #9, addr = 10002

17

O10

DAC Output #10, addr = 10012

18

O11

DAC Output #11, addr = 10102

19

O12

DAC Output #12, addr = 10112

20

VDD

Positive power supply, specified for operation at

both +3 V and +5 V

ORDERING GUIDE

Temperature

Package

Package

Model

FTN

Range

Description

Option

AD8802AN

–40°C/+85°C

PDIP-20

N-20

RS

AD8802AR

–40°C/+85°C

SOL-20

R-20

RS

AD8802ARU

–40°C/+85°C

TSSOP-20

RU-20

RS

AD8804AN

REFL

–40°C/+85°C

PDIP-20

N-20

AD8804AR

REFL

–40°C/+85°C

SOL-20

R-20

AD8804ARU

REFL

–40°C/+85°C

TSSOP-20

RU-20

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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–3–

AD8802/AD8804–Typical Performance Characteristics

	1
	0.75	VDD = +5V					TA = +85°C
		VREFH = +5V
							TA = +25°C
		VREFL = 0V					TA = –40°C
	0.5
	0.25
– LSB	0
INL	–0.25
	–0.5
	–0.75
	–1
	0	32	64	96	128	160	192	224	256

CODE – Decimal

Figure 1. INL vs. Code

	1
	0.75						TA = +85°C
							TA = +25°C
		VDD = +5V
							TA = –40°C
	0.5	VREFH = +5V
		VREFL = 0V
	0.25
LSB	0
INL –
	–0.25
	–0.5
	–0.75
	–1
	0	32	64	96	128	160	192	224	256

CODE – Decimal

Figure 2. Differential Nonlinearity Error vs. Code

	1600
										VDD = +4.5V
										VREF = +4.5V
	1280									VREFL = 0V
										TA = +25°C
										SS = 3600 PCS
FREQUENCY	960
	640
	320
	0
	0		0.2			0.4		0.6		0.8					1.0
			ABSOLUTE VALUE TOTAL UNADJUSTED ERROR – LSB

	160
	140
	120
– µA	100
CURRENT	80
	60
REF				VDD = +5V
I
	40			VREFH = +2V
				VREFL = 0V
	20			ONE DAC CHANGING WITH CODE,
				OTHER DACs SET TO 00H
				TA = +25°C
	0
	0	32	64	96	128	160	192	224	256
				CODE – Decimal

Figure 4. Input Reference Current vs. Code

	10k
nA	1k
–
CURRENT	VDD = +5.5V
	VREF = +5.5V
	100
SHUTDOWN	10
	VDD = +2.7V
	VREF = +2.7V

0	–35	–15	5	25	45	65	85	105	125
–55

TEMPERATURE – °C

Figure 5. Shutdown Current vs. Temperature

	100k
	10k						VDD = +5.5V
							VIN = +2.4V
– µA	1k
	100
CURRENT
	10
SUPPLY	1					VDD = +5.5V
						VIN = +5.5V
	0.1
	0.01
0.001
	–55	–35	–15	5	25	45	65	85	105	125
				TEMPERATURE – °C

Figure 3. Total Unadjusted Error Histogram

Figure 6. Supply Current vs. Temperature

–4–

REV. 0

	100
								TA = +25°C
	10							ALL DIGITAL INPUTS
								TIED TOGETHER
– mA	1.0							VDD = +5V
CURRENT
	0.1
SUPPLY	0.01
						VDD	= +3V
	0.001
	0.0001	0.5	1	1.5	2	2.5	3	3.5	4	4.5	5
	0
				INPUT VOLTAGE – Volts

Figure 7. Supply Current vs. Logic Input Voltage

	80
	60
				VDD = +5V
dB				ALL OUTPUTS SET
				TO MIDSCALE (80H)
–	40
PSRR
	20
	0
	10		100									1k				10k					100k

FREQUENCY – Hz

Figure 8. Power Supply Rejection vs. Frequency

6V	2V	5µs
	100
4V	90
OUT
2V
0V
		VDD = +5V
		VREF = +5V
5V	10
CS	0%
0V	0%
	5V
		TIME – 5µs/DIV

Figure 9. Large-Signal Settling Time

AD8802/AD8804

			OUTPUT1: OOH → FFH
			VDD = +5V
	– 10mV/DIV	100	VREF = +5V
		90
			f = 1MHz
	OUTPUT2	10
		0%
		10mV	200ns
			TIME – 0.2µs/DIV

Figure 10. Adjacent Channel Clock Feedthrough

	5mV	1µs
	100
OUT1	90
5mV/DIV		OUTPUT1: 7FH → 80H
		VDD = +5V
		VREF = +5V
CS
5V/DIV	10
	0%
	5V
		TIME – 1µs/DIV

			Figure 11. Midscale Transition
	0.01
LSB				VDD =	+4.5V
				VREF = +4.5V
–				SS = 176 PCS
ERRORSCALE	0
	0.005			VREFL = 0V
IN ZERO-
CHANGE	–0.005
	–0.01
			100			200		300		400		500		600
	0
					HOURS OF OPERATION AT 150°C

Figure 12. Zero-Scale Error Accelerated by Burn-In

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–5–