Analog Devices AD7249AN, AD7249SQ, AD7249BR, AD7249BN, AD7249AR Datasheet

a		LC2MOS
		Dual 12-Bit Serial DACPORT®
		AD7249

FEATURES

Two 12-Bit CMOS DAC Channels with On-Chip Voltage Reference

Output Amplifiers

Three Selectable Output Ranges per Channel –5 V to +5 V, 0 V to +5 V, 0 V to +10 V

Serial Interface

125 kHz DAC Update Rate Small Size: 16-Lead DIP or SOIC Low Power Dissipation

APPLICATIONS

Process Control

Industrial Automation

Digital Signal Processing Systems

Input/Output Ports

GENERAL DESCRIPTION

The AD7249 DACPORT contains a pair of 12-bit, voltageoutput, digital-to-analog converters with output amplifiers and Zener voltage reference on a monolithic CMOS chip. No external trims are required to achieve full specified performance.

The output amplifiers are capable of developing +10 V across a 2 kΩ load. The output voltage ranges with single supply operation are 0 V to +5 V or 0 V to +10 V, while an additional bipolar

± 5 V output range is available with dual supplies. The ranges are selected using the internal gain resistor.

Interfacing to the AD7249 is serial, minimizing pin count and allowing a small package size. Standard control signals allow interfacing to most DSP processors and microcontrollers. The data stream consists of 16 bits, DB15 to DB13 are don’t care bits, the 13th bit (DB12) is used as the channel select bit and the remaining 12 bits (DB11 to DB0) contain the data to update the DAC. The 16-bit data word is clocked into the input register on each falling SCLK edge.

The data format is natural binary in both unipolar ranges, while either offset binary or twos complement format may be selected in the bipolar range. A CLR function is provided which sets the output to 0 V in both unipolar ranges and in the twos complement bipolar range, while with offset binary data format, the output is set to –REFIN. This function is useful as a power-on reset as it allows the outputs to be set to a known voltage level.

FUNCTIONAL BLOCK DIAGRAM

	VDD		VSS
		AD7249		2R	ROFSA
REFOUT				2R
		12-BIT		A1	VOUTA
REFIN		DAC A
				2R
					ROFSB
				2R
AGND
		12-BIT		A2	VOUTB
		DAC B
DGND
	INPUT SHIFT REGISTER
SCLK	SDIN	SYNC BIN/COMP	CLR	LDAC

The AD7249 features a serial interface which allows easy connection to both microcomputers and 16-bit digital signal processors with serial ports. The serial data may be applied at rates up to 2 MHz allowing a DAC update rate of 125 kHz.

The AD7249 is fabricated on linear compatible CMOS (LC2MOS), an advanced, mixed technology process. It is packaged in 16-lead DIP and 16-lead SOIC packages.

PRODUCT HIGHLIGHTS

1.Two complete 12-bit DACPORTs

The AD7249 contains two complete voltage output, 12-bit DACs in both 16-lead DIP and SOIC packages.

2.Single or dual supply operation

3.Minimum 3-wire interface to most DSP processors

4.DAC update rate—125 kHz

DACPORT is a registered trademark of Analog Devices, Inc.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: [phone]	World Wide Web Site: http://www.analog.com
Fax: [phone]	© Analog Devices, Inc., 2000

AD7249–SPECIFICATIONS (VDD = +12 V to +15 V,1 VSS = O V or –12 V to –15 V,1 AGND = DGND = O V, REFIN = +5 V, RL = 2 k , CL = 100 pF to AGND. All specifications TMIN to TMAX unless otherwise noted.)

Parameter	A Version2	B Version2	S Version2	Unit	Test Conditions/Comments
STATIC PERFORMANCE
Resolution	12	12	12	Bits
Relative Accuracy3	± 1	± 1/2	± 1	LSB max
Differential Nonlinearity3	± 0.9	± 0.9	± 0.9	LSB max	Guaranteed Monotonic
Unipolar Offset Error3	± 5	± 5	± 6	LSB max	VSS = 0 V or –12 V to –15 V1; DAC
	± 6	± 5	± 7		Latch Contents All 0s
Bipolar Zero Error3				LSB max	VSS = –12 V to –15 V1
Full-Scale Error3, 4	± 6	± 6	± 7		DAC Latch Contents All 0s
				LSB max
Full-Scale Temperature Coefficient	± 5	± 5	± 5	ppm of FSR/°C typ
REFERENCE OUTPUT
REFOUT	4.95/5.05	4.95/5.05	4.95/5.05	V min/V max
Reference Temperature Coefficient	± 25	± 25	± 30	ppm/°C typ
Reference Load Change
(∆VREFOUT vs. IL)	–1	–1	–1	mV max	Reference Load Current (IL)
					Change (0 µA–100 µA)
REFERENCE INPUT					5 V ± 1%
Reference Input Range, REFIN	4.95/5.05	4.95/5.05	4.95/5.05	V min/V max
Input Current	5	5	5	µA max
DIGITAL INPUTS
Input High Voltage, VINH	2.4	2.4	2.4	V min
Input Low Voltage, VINL	0.8	0.8	0.8	V max
Input Current	± 1	± 1	± 1	µA max
IIN					VIN = 0 V to VDD
Input Capacitance5	8	8	8	pF max
ANALOG OUTPUTS
Output Range Resistor,				kΩ min/ max
ROFSA & ROFSB	15/30	15/30	15/30
Output Voltage Ranges6	+5, +10	+5, +10	+5, +10	V	Single Supply; VSS = 0 V
Output Voltage Ranges6	+5, +10, ± 5	+5, +10, ± 5	+5, +10, ±5	V	Dual Supply; VSS = –12 V or –15 V
DC Output Impedance	0.5	0.5	0.5	Ω typ
AC CHARACTERISTICS5
Voltage Output Settling-Time					Settling Time to Within
					± 1/2 LSB of Final Value
Positive Full-Scale Change	10	10	10	µs max	Typically 3 µs
Negative Full-Scale Change	10	10	10	µs max	Typically 5 µs
Digital-to-Analog Glitch Impulse3	30	30	30	nV secs typ	1 LSB Change Around
Digital Feedthrough3					Major Carry
	10	10	10	nV secs typ
Digital Crosstalk3	10	10	10	nV secs typ
POWER REQUIREMENTS
VDD Range	+10.8/+16.5	+11.4/+15.75	+11.4/+15.75	V min/V max	For Specified Performance Unless
					Otherwise Stated
VSS Range (Dual Supplies)	–10.8/–16.5	–11.4/–15.75	–11.4/–15.75	V min/V max	For Specified Performance Unless
					Otherwise Stated
IDD	15	15	15	mA max	Output Unloaded; Typically 11 mA
ISS (Dual Supplies)	5	5	5	mA max	Output Unloaded; Typically 3 mA

NOTES

1Power supply tolerance, A Version: ± 10%; B, S Versions: ± 5%.

2Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C. 3See Terminology.

4Measured with respect to REFIN and includes unipolar/bipolar offset error. 5Guaranteed by design not production tested.

60 V to 10 V output range available only with VDD ≥ 14.25 V. Specifications subject to change without notice.

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AD7249

TIMING CHARACTERISTICS1, 2		(VDD = +12 V to +15 V,3 VSS = 0 V or –12 V to –15 V,3 AGND = DGND = 0 V, RL = 2 k ,
		CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
	Limit at TMIN to TMAX
Parameter	(All Versions)		Unit	Conditions/Comments
t14	200		ns min	SCLK Cycle Time
t2	15		ns min	SYNC to SCLK Falling Edge Setup Time
t3	50		ns min	SYNC to SCLK Hold Time
t4	0		ns min	Data Setup Time
t5	150		ns min	Data Hold Time
t6	0		ns min	SYNC High to LDAC Low
t7	20		ns min	LDAC Pulsewidth
t8	0		ns min	LDAC High to SYNC Low
t9	50		ns min	CLR Pulsewidth
t10	20		ns min	SYNC High Time

NOTES

1Timing specifications guaranteed by design not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2See Figure 8.

3Power supply tolerance, A Version: ± 10%; B, S Versions: ± 5%. 4SCLK Mark/Space Ratio range is 45/55 to 55/45.

ABSOLUTE MAXIMUM RATINGS1

(TA = +25°C unless otherwise noted)

VDD to AGND, DGND . . . . . . . . .	. . . .	. . . . . –0.3 V to +17 V
VSS to AGND, DGND . . . . . . . . . .	. . . .	. . . . +0.3 V to –17 V
AGND to DGND . . . . . . . . . . . . . .	. . .	–0.3 V to VDD + 0.3 V
VOUTA, B2 to AGND . . . . . . . . . . . .	VSS – 0.3 V to VDD + 0.3 V
REFOUT to AGND . . . . . . . . . . . .	. . . .	. . . . . . . . 0 V to VDD
REFIN to AGND . . . . . . . . . . . . . .	. . .	–0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . .	. . .	–0.3 V to VDD + 0.3 V
Operating Temperature Range		–40°C to +85°C
Industrial (A, B Versions) . . . . . .	. . . .
Extended (S Version) . . . . . . . . . .	. . . .	. . . –55°C to +125°C
Junction Temperature . . . . . . . . . . .	. . . .	. . . . . . . . . . +150°C
Storage Temperature Range . . . . . .	. . . .	. . . –65°C to +150°C
Power Dissipation Plastic DIP . . . . .	. . . .	. . . . . . . . . . 600 mW
θJA Thermal Impedance . . . . . . . .	. . . .	. . . . . . . . +117°C/W
Lead Temperature (Soldering, 10 secs)		. . . . . . . . . . +300°C

Power Dissipation, Cerdip . . . . . . . . . . . . . . . . . . . . . . 600 mW

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 76°C/W Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +300°C

Power Dissipation, SOIC . . . . . . . . . . . . . . . . . . . . . . . 600 mW

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature (Soldering)

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one Absolute Maximum Rating may be applied at any time.

2The outputs may be shorted to voltages in this range provided the power dissipation of the package is not exceeded.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7249 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

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AD7249

		PIN FUNCTION DESCRIPTION (DIP & SOIC PIN NUMBERS)
Pin	Mnemonic	Description
1	REFOUT	Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the
		part using its internal reference, REFOUT should be connected to REFIN.
2	REFIN	Voltage Reference Input. It is internally buffered before being applied to both DACs. The nominal
		reference voltage for specified operation of the AD7249 is 5 V.
3	ROFSB	Output Offset Resistor for the amplifier of DAC B. It is connected to VOUTB for the +5 V range, to
		AGND for the +10 V range and to REFIN for the –5 V to +5 V range.
4	VOUTB	Analog Output Voltage of DAC B. This is the buffer amplifier output voltage. Three different output
		voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V.
5	AGND	Analog Ground. Ground reference for all analog circuitry.
6	CLR	Clear, Logic Input. Taking this input low clears both DACs. It sets VOUTA and VOUTB to 0 V in both
		unipolar ranges and the twos complement bipolar range and to –REFIN in the offset binary bipolar
		range.
7	BIN/COMP	Logic Input. This input selects the data format to be either binary or twos complement. In both uni-
		polar ranges natural binary format is selected by connecting this input to a Logic “0”. In the bipolar
		configuration offset binary format is selected with a Logic “0” while a Logic “1” selects twos complement.
8	DGND	Digital Ground. Ground reference for all digital circuitry.
9	SDIN	Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
10	LDAC	Load DAC, Logic Input. Updates both DAC outputs. The DAC outputs are updated on the falling
		edge of this signal or alternatively if this line is permanently low, an automatic update mode is se-
		lected whereby both DACs are updated on the 16th falling SCLK pulse.
11	SCLK	Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.
12	SYNC	Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readi-
		ness for a new data word.
13	VDD	Positive Power Supply.
14	VOUTA	Analog Output Voltage of DAC A. This is the buffer amplifier output voltage. Three different output
		voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V.
15	VSS	Negative Power Supply (used for the output amplifier only) may be connected to 0 V for single sup-
		ply operation or –12 V to –15 V for dual supplies.
16	ROFSA	Output Offset Resistor for the amplifier of DAC A. It is connected to VOUTA for the +5 V range, to
		AGND for the +10 V range and to REFIN for the –5 V to +5 V range.

PIN CONFIGURATIONS								ORDERING GUIDE
(DIP and SOIC)
								Temperature	Relative	Package
REFOUT						ROFSA	Model	Range	Accuracy	Option
	1				16		AD7249AN	–40°C to +85°C	±1 LSB	N-16
REFIN						VSS
	2				15		AD7249BN	–40°C to +85°C	±1/2 LSB	N-16
ROFSB						VOUTA
	3				14		AD7249AR	–40°C to +85°C	±1 LSB	R-16
VOUTB		AD7249				VDD
	4				13		AD7249BR	–40°C to +85°C	±1/2 LSB	R-16
		TOP VIEW
AGND	5	(Not to Scale)			12	SYNC	AD7249SQ1	–55°C to +125°C	±1 LSB	Q-16
CLR						SCLK
	6				11
							NOTE
BIN/COMP						LDAC
	7				10
							1Available to /883B processing only. Contact your local sales office for military
DGND						SDIN
	8				9		data sheet.

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