Loading...Analog Devices AD977CRS, AD977CR, AD977CN, AD977BRS, AD977BR Datasheet
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16-Bit, 100 kSPS/200 kSPS |
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BiCMOS A/D Converter |
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AD977/AD977A |
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FEATURES Fast 16-Bit ADC
100 kSPS Throughput Rate—AD977
200 kSPS Throughput Rate—AD977A Single 5 V Supply Operation
Power Dissipation 100 mW Max Power-Down Mode 50 W
Input Ranges:
Unipolar; 0 V–10 V, 0 V–5 V and 0 V–4 V Bipolar; 10 V, 5 V and 3.3 V
Choice of External or Internal 2.5 V Reference High Speed Serial Interface
On-Chip Clock
20-Lead Skinny DIP or SOIC Package
28-Lead Skinny SSOP Package
FUNCTIONAL BLOCK DIAGRAM
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REF |
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VANA |
AGND1 |
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4k |
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2.5V |
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AD977/ |
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CAP |
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REFERENCE |
AD977A |
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4R |
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R1IN |
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SYNC |
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2R |
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R2IN |
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SERIAL |
BUSY |
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R3IN |
R |
4R |
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SWITCHED |
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DATA |
DATACLK |
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CAP ADC |
INTERFACE |
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DATA |
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AGND2 |
R = 5k AD977 |
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R = 2.5k AD977A |
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VDIG |
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CONTROL LOGIC & |
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CLOCK |
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INTERNAL CALIBRATION CIRCUITRY |
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DGND |
PWRD |
R/C |
CS |
TAG |
SB/BTC EXT/INT |
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GENERAL DESCRIPTION
The AD977/AD977A is a high speed, low power 16-bit A/D converter that operates from a single 5 V supply. The AD977A has a throughput rate of 200 kSPS whereas the AD977 has a throughput rate of 100 kSPS. Each part contains a successive approximation, switched capacitor ADC, an internal 2.5 V reference, and a high speed serial interface. The ADC is factory calibrated to minimize all linearity errors. The AD977/AD977A is specified for full scale bipolar input ranges of ± 10 V, ±5 V and
± 3.3 V, and unipolar ranges of 0 V to 10 V, 0 V to 5 V and 0 V to 4 V.
The AD977/AD977A is comprehensively tested for ac parameters such as SNR and THD, as well as the more traditional dc parameters of offset, gain and linearity.
PRODUCT HIGHLIGHTS
1.Fast Throughput
The AD977/AD977A is a high speed, 16-bit ADC based on a factory calibrated switched capacitor architecture.
2.Single-Supply Operation
The AD977/AD977A operates from a single 5 V supply and dissipates only 100 mW max.
3.Comprehensive DC and AC Specifications
In addition to the traditional specifications of offset, gain and linearity, the AD977/AD977A is fully tested for SNR and THD.
REV. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 |
World Wide Web Site: http://www.analog.com |
Fax: 781/326-8703 |
© Analog Devices, Inc., 2000 |
AD977/AD977A
AD977–SPECIFICATIONS (–40 C to +85 C, FS = 100 kHz, VDIG = VANA = 5 V, unless otherwise noted)
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A Grade |
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B Grade |
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C Grade |
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Parameter |
Min |
Typ |
Max |
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Min |
Typ |
Max |
Min |
Typ |
Max |
Unit |
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RESOLUTION |
16 |
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16 |
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16 |
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Bits |
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ANALOG INPUT |
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±10 V, 0 V to 5 V, . . . (See Table II) |
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Voltage Range |
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Impedance |
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See Table II |
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Sampling Capacitance |
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40 |
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40 |
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40 |
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pF |
THROUGHPUT SPEED |
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Complete Cycle |
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10 |
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10 |
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10 |
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Throughput Rate |
100 |
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100 |
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100 |
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kHz |
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DC ACCURACY |
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±3 |
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±2.0 |
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±3 |
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LSB1 |
Integral Linearity Error |
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Differential Linearity Error |
–2 |
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+3 |
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–1 |
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+1.75 |
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±2 |
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LSB |
No Missing Codes |
15 |
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16 |
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15 |
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Bits |
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Transition Noise2 |
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1.0 |
±0.5 |
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1.0 |
±0.25 |
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1.0 |
±0.5 |
LSB |
Full-Scale Error3, 4 |
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±7 |
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±7 |
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±7 |
% |
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Full-Scale Error Drift |
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ppm/°C |
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Full-Scale Error |
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±0.5 |
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±0.25 |
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±0.5 |
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Ext. REF = 2.5 V |
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% |
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Full-Scale Error Drift |
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±2 |
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±2 |
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±2 |
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ppm/°C |
Ext. REF = 2.5 V |
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Bipolar Zero Error3 |
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±10 |
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±10 |
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±15 |
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Bipolar Ranges |
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mV |
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Bipolar Zero Error Drift |
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±2 |
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±2 |
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±2 |
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ppm/°C |
Bipolar Ranges |
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Unipolar Zero Error3 |
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±10 |
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±10 |
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±10 |
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Unipolar Ranges |
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mV |
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Unipolar Zero Error Drift |
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±2 |
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±2 |
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±2 |
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ppm/°C |
Unipolar Ranges |
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Recovery to Rated Accuracy |
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After Power-Down5 |
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2.2 F to CAP |
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1 |
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1 |
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1 |
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ms |
Power Supply Sensitivity |
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VANA = VDIG = VD = 5 V ± 5% |
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±8 |
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±8 |
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±8 |
LSB |
AC ACCURACY |
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Spurious Free Dynamic Range6 |
90 |
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96 |
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90 |
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dB7 |
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Total Harmonic Distortion6 |
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–90 |
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–96 |
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–90 |
dB |
Signal-to-(Noise+Distortion)6 |
83 |
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85 |
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83 |
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dB |
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–60 dB Input |
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27 |
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28 |
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27 |
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dB |
Signal-to-Noise6 |
83 |
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85 |
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83 |
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dB |
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Full Power Bandwidth8 |
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700 |
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700 |
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700 |
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kHz |
–3 dB Input Bandwidth |
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1.5 |
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1.5 |
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1.5 |
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MHz |
SAMPLING DYNAMICS |
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Aperture Delay |
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40 |
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40 |
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40 |
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ns |
Transient Response, Full-Scale Step |
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2 |
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2 |
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2 |
s |
Overvoltage Recovery9 |
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150 |
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150 |
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150 |
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REFERENCE |
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Internal Reference Voltage |
2.48 |
2.5 |
2.52 |
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2.48 |
2.5 |
2.52 |
2.48 |
2.5 |
2.52 |
V |
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Internal Reference Source Current |
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1 |
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1 |
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1 |
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A |
External Reference Voltage Range |
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for Specified Linearity |
2.3 |
2.5 |
2.7 |
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2.3 |
2.5 |
2.7 |
2.3 |
2.5 |
2.7 |
V |
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External Reference Current Drain |
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A |
Ext. REF = 2.5 V |
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100 |
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100 |
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100 |
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NOTES
1LSB means Least Significant Bit. With a ±10 V input, one LSB is 305 µV. 2Typical rms noise at worst case transitions and temperatures.
3Measured with fixed resistors as shown in Figures 11, 12 and 13. Adjustable to zero. Tested at room temperature.
4Full-Scale Error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full scale transition voltage, and includes the effect of offset error. For bipolar input ranges, the Full-Scale Error is the worst case of either the –Full Scale or +Full Scale code transition voltage errors. For unipolar input ranges, Full-Scale Error is with respect to the +Full-Scale code transition voltage.
5External 2.5 V reference connected to REF.
6fIN = 20 kHz, 0.5 dB down unless otherwise noted.
7All specifications in dB are referred to a full scale ±10 V input.
8Full-Power Bandwidth is defined as full-scale input frequency at which Signal-to-(Noise+Distortion) degrades to 60 dB, or 10 bits of accuracy. 9Recovers to specified performance after a 2 × FS input overvoltage.
Specifications subject to change without notice.
–2– |
REV. D |
AD977/AD977A
AD977A–SPECIFICATIONS(–40 C to +85 C, FS = 200 kHz, VDIG = VANA = 5 V, unless otherwise noted)
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A Grade |
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B Grade |
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C Grade |
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Parameter |
Min |
Typ |
Max |
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Min |
Typ |
Max |
Min |
Typ |
Max |
Unit |
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RESOLUTION |
16 |
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16 |
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16 |
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Bits |
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ANALOG INPUT |
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±10 V, 0 V to 5 V, . . . (See Table II) |
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Voltage Range |
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Impedance |
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See Table II |
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Sampling Capacitance |
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40 |
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40 |
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40 |
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pF |
THROUGHPUT SPEED |
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s |
Complete Cycle |
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5 |
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5 |
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5 |
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Throughput Rate |
200 |
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200 |
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200 |
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kHz |
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DC ACCURACY |
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±3 |
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±2.0 |
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±3 |
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LSB1 |
Integral Linearity Error |
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Differential Linearity Error |
–2 |
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+3 |
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–1 |
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+1.75 |
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±2 |
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LSB |
No Missing Codes |
15 |
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16 |
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15 |
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Bits |
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Transition Noise2 |
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1.0 |
±0.5 |
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1.0 |
±0.25 |
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1.0 |
±0.5 |
LSB |
Full-Scale Error3, 4 |
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±7 |
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±7 |
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±7 |
% |
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Full-Scale Error Drift |
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ppm/°C |
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Full-Scale Error |
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±0.5 |
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±0.25 |
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±0.5 |
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Ext. REF = 2.5 V |
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% |
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Full-Scale Error Drift |
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±2 |
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±2 |
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±2 |
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ppm/°C |
Ext. REF = 2.5 V |
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Bipolar Zero Error3 |
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±10 |
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±10 |
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±15 |
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Bipolar Ranges |
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mV |
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Bipolar Zero Error Drift |
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±2 |
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±2 |
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±2 |
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ppm/°C |
Bipolar Ranges |
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Unipolar Zero Error3 |
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±10 |
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±10 |
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±10 |
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Unipolar Ranges |
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mV |
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Unipolar Zero Error Drift |
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±2 |
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±2 |
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±2 |
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ppm/°C |
Unipolar Ranges |
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Recovery to Rated Accuracy |
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After Power-Down5 |
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2.2 F to CAP |
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1 |
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1 |
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1 |
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ms |
Power Supply Sensitivity |
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VANA = VDIG = VD = 5 V ± 5% |
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±8 |
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±8 |
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±8 |
LSB |
AC ACCURACY |
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Spurious Free Dynamic Range6 |
90 |
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96 |
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90 |
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dB7 |
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Total Harmonic Distortion6 |
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–90 |
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–96 |
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–90 |
dB |
Signal-to-(Noise+Distortion)6 |
83 |
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85 |
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83 |
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dB |
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–60 dB Input |
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27 |
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28 |
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27 |
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dB |
Signal-to-Noise6 |
83 |
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85 |
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83 |
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dB |
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Full Power Bandwidth8 |
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1 |
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1 |
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1 |
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MHz |
–3 dB Input Bandwidth |
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2.7 |
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2.7 |
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2.7 |
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MHz |
SAMPLING DYNAMICS |
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Aperture Delay |
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40 |
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40 |
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40 |
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ns |
Transient Response, Full-Scale Step |
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1 |
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1 |
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1 |
s |
Overvoltage Recovery9 |
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150 |
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150 |
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150 |
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ns |
REFERENCE |
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Internal Reference Voltage |
2.48 |
2.5 |
2.52 |
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2.48 |
2.5 |
2.52 |
2.48 |
2.5 |
2.52 |
V |
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Internal Reference Source Current |
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1 |
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1 |
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1 |
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A |
External Reference Voltage Range |
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for Specified Linearity |
2.3 |
2.5 |
2.7 |
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2.3 |
2.5 |
2.7 |
2.3 |
2.5 |
2.7 |
V |
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External Reference Current Drain |
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Ext. REF = 2.5 V |
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1.2 |
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1.2 |
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1.2 |
mA |
NOTES
1LSB means Least Significant Bit. With a ±10 V input, one LSB is 305 µV. 2Typical rms noise at worst case transitions and temperatures.
3Measured with fixed resistors as shown in Figures 11, 12 and 13. Adjustable to zero. Tested at room temperature.
4Full-Scale Error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full scale transition voltage, and includes the effect of offset error. For bipolar input ranges, the Full-Scale Error is the worst case of either the –Full Scale or +Full Scale code transition voltage errors. For unipolar input ranges, Full-Scale Error is with respect to the +Full-Scale code transition voltage.
5External 2.5 V reference connected to REF.
6fIN = 20 kHz, 0.5 dB down unless otherwise noted.
7All specifications in dB are referred to a full scale ±10 V input.
8Full-Power Bandwidth is defined as full-scale input frequency at which Signal-to-(Noise+Distortion) degrades to 60 dB, or 10 bits of accuracy. 9Recovers to specified performance after a 2 × FS input overvoltage.
Specifications subject to change without notice.
REV. D |
–3– |
AD977/AD977A–SPECIFICATIONS (Both Specs)
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A, B, C Grades |
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Parameter |
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Conditions |
Min |
Typ |
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Max |
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Unit |
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DIGITAL INPUTS |
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Logic Levels |
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VIL |
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–0.3 |
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+0.8 |
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V |
VIH |
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2.0 |
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VDIG + 0.3 |
V |
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IIL |
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± 10 |
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A |
IIH |
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± 10 |
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A |
DIGITAL OUTPUTS |
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Data Format |
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Serial 16-Bits |
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Data Coding |
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Binary Two’s Complement or Straight Binary |
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Pipeline Delay |
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Conversion Results Only Available after Completed Conversion |
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VOL |
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ISINK = 1.6 mA |
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0.4 |
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V |
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VOH |
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ISOURCE = 500 A |
4 |
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V |
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POWER SUPPLIES |
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Specified Performance |
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VDIG |
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4.75 |
5 |
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5.25 |
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V |
VANA |
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4.75 |
5 |
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5.25 |
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V |
IDIG |
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4 |
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mA |
IANA |
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11 |
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mA |
Power Dissipation |
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PWRD LOW |
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100 |
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mW |
PWRD HIGH |
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50 |
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W |
TEMPERATURE RANGE |
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°C |
Specified Performance |
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TMIN to TMAX |
–40 |
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+85 |
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Specifications subject to change without notice. |
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TIMING SPECIFICATIONS (AD977A: FS = 200 kHz, AD977: FS = 100 kHz, VDIG = VANA = 5 V, –40 C to +85 C) |
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AD977A |
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AD977 |
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Symbol |
Min Typ |
Max |
Min Typ |
Max |
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Unit |
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Convert Pulsewidth |
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t1 |
50 |
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50 |
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ns |
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R/C, CS to BUSY Delay |
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t2 |
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83 |
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83 |
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ns |
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BUSY LOW Time |
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t3 |
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4.0 |
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8.0 |
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s |
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BUSY Delay after End of Conversion |
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t4 |
50 |
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50 |
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ns |
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Aperture Delay |
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t5 |
40 |
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40 |
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ns |
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Conversion Time |
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t6 |
3.8 |
4.0 |
7.6 |
8.0 |
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s |
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Acquisition Time |
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t7 |
1.0 |
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2.0 |
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s |
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Throughput Time |
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t6 + t7 |
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5 |
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10 |
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s |
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R/C Low to DATACLK Delay |
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t8 |
220 |
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350 |
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ns |
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DATACLK Period |
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t9 |
220 |
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450 |
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ns |
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DATA Valid Setup Time |
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t10 |
50 |
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100 |
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ns |
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DATA Valid Hold Time |
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t11 |
20 |
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20 |
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ns |
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EXT. DATACLK Period |
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t12 |
66 |
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100 |
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ns |
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EXT. DATACLK HIGH |
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t13 |
20 |
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20 |
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ns |
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EXT. DATACLK LOW |
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t14 |
30 |
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30 |
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ns |
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R/C, CS to EXT. DATACLK Setup Time |
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t15 |
20 |
t12 + 5 |
20 |
t12 + 5 |
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ns |
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R/C to CS Setup Time |
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t16 |
10 |
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10 |
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ns |
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EXT. DATACLK to SYNC Delay |
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t17 |
15 |
66 |
15 |
66 |
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ns |
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EXT. DATACLK to DATA Valid Delay |
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t18 |
25 |
66 |
25 |
66 |
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CS to EXT. DATACLK Rising Edge Delay |
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t19 |
10 |
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10 |
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ns |
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Previous DATA Valid after CS, R/C Low |
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t20 |
3.5 |
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7.5 |
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s |
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BUSY to EXT. DATACLK Setup Time |
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t21 |
5 |
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5 |
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ns |
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Final EXT. DATACLK to BUSY Rising Edge |
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t22 |
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1.7 |
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3.5 |
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s |
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TAG Valid Setup Time |
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t23 |
0 |
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0 |
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ns |
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TAG Valid Hold Time |
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t24 |
20 |
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20 |
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ns |
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Specifications subject to change without notice.
–4– |
REV. D |
AD977/AD977A
ABSOLUTE MAXIMUM RATINGS1
Analog Inputs
R1IN, R2IN , R3IN . . . . . . . |
. . . . . . |
. . . . . . . . . . . . . . . ±25 V |
CAP . . . . . . . . . . . . . . . . . |
+VANA + 0.3 V to AGND2 – 0.3 V |
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REF . . . . . . . . . . . . . . . . . |
. . . . Indefinite Short to AGND2, |
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Ground. . .Voltage. . . . . .Differences. . . . . . . . . . |
. . . . . . |
Momentary Short to VANA |
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±0.3 V |
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DGND, AGND1, AGND2 . . . . . . |
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Supply Voltages |
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VANA . . . . . . . . . . . . . . . . |
. . . . . . . |
. . . . . . . . . . . . . . . . 7 V |
VDIG to VANA . . . . . . . . . . |
. . . . . . . |
. . . . . . . . . . . . . . . ±7 V |
VDIG . . . . . . . . . . . . . . . . |
. . . . . . . |
. . . . . . . . . . . . . . . . 7 V |
Digital Inputs . . . . . . . . . . . |
. . . . . . . |
. –0.3 V to VDIG + 0.3 V |
Internal Power Dissipation2 |
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PDIP (N), SOIC (R), SSOP (RS) . |
. . . . . . . . . . . . 700 mW |
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Junction Temperature . . . . . |
. . . . . . . |
. . . . . . . . . . . . . . 150°C |
Storage Temperature Range N, R . . . |
. . . . . –65°C to +150°C |
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Lead Temperature Range |
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300°C |
(Soldering 10 sec) . . . . . . |
. . . . . . . |
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NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2Specification is for device in free air:
20-Lead PDIP: θJA = 100°C/W, θJC = 31°C/W,
20-Lead SOIC: θJA = 75°C/W, θJC = 24°C/W,
28-Lead SSOP: θJA = 109°C/W, θJC = 39°C/W.
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PIN CONFIGURATIONS |
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SOIC and DIP |
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SSOP |
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R1IN |
1 |
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20 |
VDIG |
R1IN |
1 |
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28 |
VDIG |
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AGND1 |
2 |
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27 |
VANA |
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AGND1 |
2 |
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19 |
VANA |
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R2IN |
3 |
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26 |
PWRD |
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R2IN |
3 |
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18 |
PWRD |
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R3IN |
4 |
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25 |
BUSY |
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R3IN |
4 |
AD977 |
17 |
BUSY |
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5 |
AD977A |
16 |
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NC |
5 |
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24 CS |
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CAP |
CS |
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TOP VIEW |
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CAP |
6 |
AD977 |
23 |
NC |
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REF |
6 |
(Not to Scale) |
15 |
R/C |
REF |
7 |
AD977A |
22 |
NC |
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AGND2 |
7 |
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14 |
TAG |
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NC |
8 |
TOP VIEW |
21 |
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(Not to Scale) |
R/C |
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SB/BTC |
8 |
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13 |
DATA |
AGND2 |
9 |
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20 |
NC |
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EXT/INT |
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9 |
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12 |
DATACLK |
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NC |
10 |
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19 |
TAG |
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DGND |
10 |
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11 |
SYNC |
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NC |
11 |
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18 |
NC |
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SB/BTC |
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17 |
DATA |
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EXT/INT |
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13 |
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16 |
DATACLK |
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SYNC |
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DGND |
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15 |
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NC = NO CONNECT |
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1.6mA 
IOL
TO OUTPUT
PIN
1.4V CL 
100pF
500 A 
IOH
Figure 1. Load Circuit for Digital Interface Timing
ORDERING GUIDE
|
Temperature |
Throughput |
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Package |
Model |
Range |
Rate |
Max INL |
Min S/(N+D) |
Options* |
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AD977AN |
–40°C to +85°C |
100 kSPS |
± 3.0 LSB |
83 dB |
N-20 |
AD977BN |
–40°C to +85°C |
100 kSPS |
± 2.0 LSB |
85 dB |
N-20 |
AD977CN |
–40°C to +85°C |
100 kSPS |
± 3.0 LSB |
83 dB |
N-20 |
AD977AAN |
–40°C to +85°C |
200 kSPS |
83 dB |
N-20 |
|
AD977ABN |
–40°C to +85°C |
200 kSPS |
± 2.0 LSB |
85 dB |
N-20 |
AD977ACN |
–40°C to +85°C |
200 kSPS |
|
83 dB |
N-20 |
AD977AR |
–40°C to +85°C |
100 kSPS |
± 3.0 LSB |
83 dB |
R-20 |
AD977BR |
–40°C to +85°C |
100 kSPS |
± 2.0 LSB |
85 dB |
R-20 |
AD977CR |
–40°C to +85°C |
100 kSPS |
± 3.0 LSB |
83 dB |
R-20 |
AD977AAR |
–40°C to +85°C |
200 kSPS |
83 dB |
R-20 |
|
AD977ABR |
–40°C to +85°C |
200 kSPS |
± 2.0 LSB |
85 dB |
R-20 |
AD977ACR |
–40°C to +85°C |
200 kSPS |
|
83 dB |
R-20 |
AD977ARS |
–40°C to +85°C |
100 kSPS |
± 3.0 LSB |
83 dB |
RS-28 |
AD977BRS |
–40°C to +85°C |
100 kSPS |
± 2.0 LSB |
85 dB |
RS-28 |
AD977CRS |
–40°C to +85°C |
100 kSPS |
± 3.0 LSB |
83 dB |
RS-28 |
AD977AARS |
–40°C to +85°C |
200 kSPS |
83 dB |
RS-28 |
|
AD977ABRS |
–40°C to +85°C |
200 kSPS |
± 2.0 LSB |
85 dB |
RS-28 |
AD977ACRS |
–40°C to +85°C |
200 kSPS |
|
83 dB |
RS-28 |
*N = 20-lead 300 mil plastic DIP; R = 20-lead SOIC; RS = 28-lead SSOP.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD977/AD977A feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D |
–5– |
AD977/AD977A
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PIN FUNCTION DESCRIPTIONS |
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Pin No. |
Pin No. |
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DIP/SOIC |
SSOP |
Mnemonic |
Description |
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1, 3, 4 |
1, 3, 4 |
R1IN, R2IN, R3IN |
Analog Input. Refer to Table I, Table II for input range configuration. |
2 |
2 |
AGND1 |
Analog Ground. Used as the ground reference point for the REF pin. |
5 |
6 |
CAP |
Reference buffer output. Connect a 2.2 F tantalum capacitor between CAP and |
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Analog Ground. |
6 |
7 |
REF |
Reference Input/Output. The internal 2.5 V reference is available at this pin. |
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Alternatively an external reference can be used to override the internal reference. In |
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either case, connect a 2.2 F tantalum capacitor between REF and Analog Ground. |
7 |
9 |
AGND2 |
Analog Ground. |
8 |
12 |
SB/BTC |
This digital input is used to select the data format of a conversion result. With SB/BTC |
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tied LOW, conversion data will be output in Binary Two’s Complement format. With |
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SB/BTC connected to a logic HIGH, data is output in Straight Binary format. |
9 |
13 |
EXT/INT |
Digital select input for choosing the internal or an external data clock. With EXT/INT |
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tied LOW, after initiating a conversion, 16 DATACLK pulses transmit the previous |
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conversion result as shown in Figure 3. With EXT/INT set to a logic HIGH, output |
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data is synchronized to an external clock signal connected to the DATACLK input. |
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Data is output as indicated in Figure 4 through Figure 9. |
10 |
14 |
DGND |
Digital Ground. |
11 |
15 |
SYNC |
Digital output frame synchronization for use with an external data clock |
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(EXT/INT = Logic HIGH). When a read sequence is initiated, a pulse one |
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DATACLK period wide is output synchronous to the external data clock. |
12 |
16 |
DATACLK |
Serial data clock input or output, dependent upon the logic state of the EXT/INT |
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pin. When using the internal data clock (EXT/INT = Logic LOW), a conversion |
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start sequence will initiate transmission of 16 DATACLK periods. Output data is |
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synchronous to this clock and is valid on both its rising and falling edges (Figure 3). |
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When using an external data clock (EXT/INT = Logic HIGH), the CS and R/C |
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signals control how conversion data is accessed. |
13 |
17 |
DATA |
The serial data output is synchronized to DATACLK. Conversion results are |
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stored in an on-chip register. The AD977 provides the conversion result, MSB first, |
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from its internal shift register. The DATA format is determined by the logic level of |
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SB/BTC. When using the internal data clock (EXT/INT = Logic LOW), DATA is |
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valid on both the rising and falling edges of DATACLK. Between conversions |
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DATA will remain at the level of the TAG input when the conversion was started. |
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Using an external data clock (EXT/INT = Logic HIGH) allows previous conversion |
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data to be accessed during a conversion (Figures 5, 7 and 9) or the conversion |
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result can be accessed after the completion of a conversion (Figures 4, 6 and 8). |
14 |
19 |
TAG |
This digital input can be used with an external data clock, (EXT/INT = Logic |
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HIGH) to daisy chain the conversion results from two or more AD977s onto a |
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single DATA line. The digital data level on TAG is output on DATA with a delay |
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of 16 or 17 external DATACLK periods after the initiation of the read sequence. |
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Dependent on whether a SYNC is not present or present. |
15 |
21 |
R/C |
Read/Convert Input. Is used to control the conversion and read modes of the |
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AD977. With CS LOW; a falling edge on R/C holds the analog input signal inter- |
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nally and starts a conversion, a rising edge enables the transmission of the conver- |
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sion result. |
16 |
24 |
CS |
Chip Select Input. With R/C LOW, a falling edge on CS will initiate a conversion. |
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With R/C HIGH, a falling edge on CS will enable the serial data output sequence. |
17 |
25 |
BUSY |
Busy Output. Goes LOW when a conversion is started, and remains LOW until the |
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conversion is completed and the data is latched into the on-chip shift register. |
18 |
26 |
PWRD |
Power-Down Input. When set to a logic HIGH power consumption is reduced and |
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conversions are inhibited. The conversion result from the previous conversion is |
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stored in the onboard shift register. |
19 |
27 |
VANA |
Analog Power Supply. Nominally 5 V. |
20 |
28 |
VDIG |
Digital Power Supply. Nominally 5 V. |
–6– |
REV. D |
AD977/AD977A
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL)
Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.
FULL-SCALE ERROR
The last + transition (from 011 . . . 10 to 011 . . . 11 for two’s complement format) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (9.9995422 V for a ±10 V range). The full-scale error is the deviation of the actual level of the last transition from the ideal level.
BIPOLAR ZERO ERROR
Bipolar zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code.
UNIPOLAR ZERO ERROR
In unipolar mode, the first transition should occur at a level 1/2 LSB above analog ground. Unipolar zero error is the deviation of the actual transition from that point.
SPURIOUS FREE DYNAMIC RANGE
The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of a full-scale input signal and is expressed in decibels.
SIGNAL TO (NOISE AND DISTORTION) (S/[N+D]) RATIO
S/(N+D) is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels.
FULL POWER BANDWIDTH
The full power bandwidth is defined as the full-scale input frequency at which the S/(N+D) degrades to 60 dB, 10 bits of accuracy.
APERTURE DELAY
Aperture delay is a measure of the acquisition performance, and is measured from the falling edge of the R/C input to when the input signal is held for a conversion.
TRANSIENT RESPONSE
The time required for the AD977/AD977A to achieve its rated accuracy after a full-scale step function is applied to its input.
OVERVOLTAGE RECOVERY
The time required for the ADC to recover to full accuracy after an analog input signal 150% of full-scale is reduced to 50% of the full-scale value.
REV. D |
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AD977/AD977A
CONVERSION CONTROL
The AD977/AD977A is controlled by two signals: R/C and CS. When R/C is brought low, with CS low, for a minimum of 50 ns, the input signal will be held on the internal capacitor array and a conversion “n” will begin. Once the conversion process does begin, the BUSY signal will go low until the conversion is complete. Internally, the signals R/C and CS are OR’d together and there is no requirement on which signal is taken low first when initiating a conversion. The only requirement is that there be at least 10 ns of delay between the two signals being taken low. After the conversion is complete the BUSY signal will return high and the AD977/AD977A will again resume tracking the input signal. Under certain conditions the CS pin can be tied Low and R/C will be used to determine whether you are initiating a conversion or reading data. On the first conversion, after the AD977/AD977A is powered up, the DATA output will be indeterminate.
Conversion results can be clocked serially out of the AD977/ AD977A using either an internal clock, generated by the AD977/AD977A, or by using an external clock. The AD977/ AD977A is configured for the internal data clock mode by pulling the EXT/INT pin low. It is configured for the external clock mode by pulling the EXT/INT pin high.
INTERNAL DATA CLOCK MODE
The AD977/AD977A is configured to generate and provide the data clock when the EXT/INT pin is held low. Typically CS will be tied low and R/C will be used to initiate a conversion “n.” During the conversion the AD977/AD977A will output 16 bits of data, MSB first, from conversion “n-1” on the DATA pin. This data will be synchronized with 16 clock pulses provided on the DATACLK pin. The output data will be valid on both the rising and falling edge of the data clock as shown in Figure 3. After the LSB has been presented, the DATA pin will assume whatever state the TAG input was at during the start of conversion, and the DATACLK pin will stay low until another conversion is initiated.
EXTERNAL DATA CLOCK MODE
The AD977/AD977A is configured to accept an externally supplied data clock when the EXT/INT pin is held high. This mode of operation provides several methods by which conversion results can be read from the AD977/AD977A. The output data from conversion “n-1” can be read during conversion “n,” or the output data from conversion “n” can be read after the conversion is complete. The external clock can be either a continuous or discontinuous clock. A discontinuous clock can be either
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CS, R/C |
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t3 |
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BUSY |
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t5 |
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MODE |
ACQUIRE |
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CONVERT |
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ACQUIRE |
CONVERT |
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Figure 2. Basic Conversion Timing |
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R/C |
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t9 |
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DATACLK |
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DATA |
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MSB VALID |
BIT 14 |
BIT 13 |
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LSB VALID |
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VALID |
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VALID |
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t2 |
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t6 |
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BUSY
Figure 3. Serial Data Timing for Reading Previous Conversion Results with Internal Clock (CS, EXT/ INT and TAG Set to Logic Low)
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REV. D |
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